The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2020

Filed:

Apr. 04, 2016
Applicant:

Pdf Solutions, Inc., San Jose, CA (US);

Inventors:

Stephen Lam, Freemont, CA (US);

Dennis Ciplickas, San Jose, CA (US);

Tomasz Brozek, Morgan Hill, CA (US);

Jeremy Cheng, San Jose, CA (US);

Simone Comensoli, Darfo Boario Terme, IT;

Indranil De, Mountain View, CA (US);

Kelvin Doong, Hsinchu, TW;

Hans Eisenmann, Tutzing, DE;

Timothy Fiscus, New Galilee, PA (US);

Jonathan Haigh, Pittsburgh, PA (US);

Christopher Hess, Belmont, CA (US);

John Kibarian, Los Altos Hills, CA (US);

Sherry Lee, Monte Sereno, CA (US);

Marci Liao, Santa Clara, CA (US);

Sheng-Che Lin, Hsinchu, TW;

Hideki Matsuhashi, Santa Clara, CA (US);

Kimon Michaels, Monte Sereno, CA (US);

Conor O'Sullivan, Campbell, CA (US);

Markus Rauscher, Munich, DE;

Vyacheslav Rovner, Pittsburgh, PA (US);

Andrzej Strojwas, Pittsburgh, PA (US);

Marcin Strojwas, Pittsburgh, PA (US);

Carl Taylor, Pittsburgh, PA (US);

Rakesh Vallishayee, Dublin, CA (US);

Larg Weiland, Hollister, CA (US);

Nobuharu Yokoyama, Tokyo, JP;

Assignee:

PDF Solutions, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 27/02 (2006.01); G06K 9/03 (2006.01); G06K 9/62 (2006.01); G01R 31/307 (2006.01); G01N 21/956 (2006.01); H01L 23/544 (2006.01); G01R 31/28 (2006.01); G01N 21/66 (2006.01); G06T 7/00 (2017.01);
U.S. Cl.
CPC ...
H01L 22/34 (2013.01); G01N 21/66 (2013.01); G01N 21/956 (2013.01); G01R 31/2884 (2013.01); G01R 31/307 (2013.01); G06K 9/033 (2013.01); G06K 9/6202 (2013.01); G06T 7/001 (2013.01); H01L 23/544 (2013.01);
Abstract

Improved processes for manufacturing wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements ('NCEM') of fill cells that contain structures configured target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such processes may involve evaluating Designs of Experiments ('DOEs'), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).


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