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Santa Clara, CA, United States of America

Hideki Matsuhashi

This inventor holds 82 USPTO granted patents, primarily in Semiconductor Technology (CPC class H01L27-0207). Top assignee: Pdf Solutions, Incorporated. Active years: 2017-2021.

USPTO Granted Patents = 82

% Patents Active = 4.9

Average Co-Inventor Count = 26.0

ph-index = 8

Forward Citations = 255(Granted Patents)

Forward Citations (Not Self Cited) = 202(Dec 10, 2025)

Inventors with similar research interests:

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Company Filing History:

82 out of 203

Pdf Solutions, Incorporated

patents

Years Active: 2017-2021

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Areas of Expertise:

Non-Contact Measurements

Integrated Circuit

Semiconductor Wafer

Test Structures

NCEM-Enabled Fill Cells

Electrical Measurements

Tip-to-Side Short

Corner Short

Chamfer Short

Resistance Configured Fill Cells

Standard Cell Compatible

GATECNT

82 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 11107804 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-31),

2. 11081477 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-03),

3. 11081476 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-03),

4. 11075194 - IC with test structures and E-beam pads embedded within a contiguous standard cell area (2021-07-27),

5. 11018126 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-05-25),

6. 10978438 - IC with test structures and E-beam pads embedded within a contiguous standard cell area (2021-04-13),

7. 10854522 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas (2020-12-01),

8. 10777472 - IC with test structures embedded within a contiguous standard cell area (2020-09-15),

9. 10593604 - Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells (2020-03-17),

10. 10290552 - Methods for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage (2019-05-14),

11. 10269786 - Integrated circuit containing first and second DOEs of standard Cell Compatible, NCEM-enabled Fill Cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including corner short configured fill cells (2019-04-23),

12. 10211112 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas (2019-02-19),

13. 10211111 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side sort, and corner short test areas (2019-02-19),

14. 10199294 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage (2019-02-05),

15. 10199293 - Method for processing a semiconductor water using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, side to side short, and chamfer short test areas (2019-02-05),

Title: The Innovative Journey of Hideki Matsuhashi

Introduction:

Hideki Matsuhashi, a pioneering inventor based in Santa Clara, CA, has made significant contributions to the world of technology through his groundbreaking innovations and patents.

Latest Patents:

Matsuhashi's latest patents focus on advancements in artificial intelligence algorithms for autonomous vehicles, revolutionizing the way we perceive transportation and safety on the roads.

Career Highlights:

With a career spanning over two decades, Hideki Matsuhashi has worked with renowned tech companies in Silicon Valley, leading research and development teams to create cutting-edge solutions in the fields of robotics, machine learning, and computer vision.

Collaborations:

Throughout his career, Matsuhashi has collaborated with top engineers, scientists, and researchers from prestigious universities and research institutions worldwide, fostering a culture of innovation and excellence in every project he undertakes.

Conclusion:

Hideki Matsuhashi's relentless pursuit of innovation and his passion for pushing the boundaries of technology have solidified his reputation as a visionary inventor in the ever-evolving landscape of the tech industry.

Profile summary based on public USPTO records.

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