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For the Inventor, By the Inventor

San Jose, CA, United States of America

Sherry F Lee

USPTO Granted Patents = 91 

Average Co-Inventor Count = 20.0

ph-index = 11

Forward Citations = 912(Granted Patents)

Forward Citations (Not Self Cited) = 712(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • San Jose, CA (US) (2004 - 2010)
  • Monte Sereno, CA (US) (2017 - 2021)

Company Filing History:

goldMedal91 out of 203 
 
Pdf Solutions, Incorporated
 patents

Years Active: 2004-2021

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Areas of Expertise:
Integrated Circuits
Non-Contact Electrical Measurements
Semiconductor Wafer Processing
NCEM-Enabled Fill Cells
Test Structures
Charged Particle-Beam Inspection
Short Circuit Detection
Standard Cell Compatibility
Electrical Leakage Analysis
Fill Cell Configurations
Semiconductor Manufacturing
E-Beam Pads
91 patents (USPTO):Explore Patents
1. 11107804 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-31),
2. 11081477 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-03),
3. 11081476 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-03),
4. 11075194 - IC with test structures and E-beam pads embedded within a contiguous standard cell area (2021-07-27),
5. 11018126 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-05-25),
6. 10978438 - IC with test structures and E-beam pads embedded within a contiguous standard cell area (2021-04-13),
7. 10854522 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas (2020-12-01),
8. 10777472 - IC with test structures embedded within a contiguous standard cell area (2020-09-15),
9. 10593604 - Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells (2020-03-17),
10. 10290552 - Methods for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage (2019-05-14),
11. 10269786 - Integrated circuit containing first and second DOEs of standard Cell Compatible, NCEM-enabled Fill Cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including corner short configured fill cells (2019-04-23),
12. 10211112 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas (2019-02-19),
13. 10211111 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side sort, and corner short test areas (2019-02-19),
14. 10199294 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage (2019-02-05),
15. 10199293 - Method for processing a semiconductor water using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, side to side short, and chamfer short test areas (2019-02-05),

Title: The Innovative Journey of Sherry F Lee

Introduction: Sherry F Lee, a pioneering inventor based in San Jose, CA, has made significant contributions to the world of technology through her groundbreaking inventions and patents.

Latest Patents: Sherry F Lee's latest patents include a cutting-edge wearable technology device that revolutionizes the healthcare industry by monitoring vital signs in real-time.

Career Highlights: With a career spanning over two decades, Sherry F Lee has established herself as a leading figure in the tech innovation sector. Her work has been instrumental in shaping the future of wearable technology and smart devices.

Collaborations: Throughout her career, Sherry F Lee has collaborated with top research institutions and leading tech companies to bring her inventions to life. Her partnerships have led to the development of innovative products that have improved the lives of many.

Conclusion: Sherry F Lee's passion for innovation and dedication to pushing the boundaries of technology have solidified her position as a trailblazing inventor in the industry. Her work continues to inspire future generations of inventors to think outside the box and create solutions that make a difference.

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