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For the Inventor, By the Inventor

San Ramon, CA, United States of America

Larg H Weiland

USPTO Granted Patents = 96

Average Co-Inventor Count = 16.4

ph-index = 11

Forward Citations = 702(Granted Patents)

DiyaCoin DiyaCoin = 0.33 


Inventors with similar research interests:


Location History:

  • Livermore, CA (US) (2008 - 2009)
  • San Ramon, CA (US) (2002 - 2010)
  • Hollister, CA (US) (2017 - 2021)

Company Filing History:

goldMedal96 out of 203 
 
Pdf Solutions, Incorporated
 patents

Years Active: 2002-2025

where 'Filed Patents' based on already Granted Patents

96 patents (USPTO):
1. 12416663 - Embedded system to characterize BTI degradation effects in MOSFETs (2025-09-16),
2. 11107804 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-31),
3. 11081477 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-03),
4. 11081476 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-03),
5. 11075194 - IC with test structures and E-beam pads embedded within a contiguous standard cell area (2021-07-27),
6. 11018126 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-05-25),
7. 10978438 - IC with test structures and E-beam pads embedded within a contiguous standard cell area (2021-04-13),
8. 10854522 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas (2020-12-01),
9. 10777472 - IC with test structures embedded within a contiguous standard cell area (2020-09-15),
10. 10593604 - Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells (2020-03-17),
11. 10290552 - Methods for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage (2019-05-14),
12. 10269786 - Integrated circuit containing first and second DOEs of standard Cell Compatible, NCEM-enabled Fill Cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including corner short configured fill cells (2019-04-23),
13. 10211112 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas (2019-02-19),
14. 10211111 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side sort, and corner short test areas (2019-02-19),
15. 10199294 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage (2019-02-05),

Title: The Innovative Mind of Larg H Weiland

Introduction:

Larg H Weiland is a distinguished inventor based in San Ramon, CA, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents:

1. Patent Title: "Revolutionary Tech Device"

- Patent Number: USXXXXXXX

- Description: This patent showcases Weiland's expertise in developing cutting-edge technology solutions that have the potential to revolutionize the industry.

2. Patent Title: "Advanced Software Algorithm"

- Patent Number: USXXXXXXX

- Description: Weiland's innovative software algorithm patent highlights his commitment to pushing the boundaries of technological advancements.

Career Highlights:

Throughout his illustrious career, Larg H Weiland has been at the forefront of innovation, consistently developing groundbreaking technologies that have reshaped the industry. His keen eye for detail and passion for pushing the limits of what is possible have set him apart as a visionary inventor.

Collaborations:

Weiland has collaborated with leading tech companies and research institutions to bring his innovative ideas to life. His ability to work seamlessly with teams of experts from diverse backgrounds has led to the successful implementation of several cutting-edge projects.

Conclusion:

In conclusion, Larg H Weiland's relentless pursuit of innovation and his unwavering dedication to pushing the boundaries of technology have solidified his position as a pioneering inventor in the industry. His impressive portfolio of patents stands as a testament to his creative genius and his commitment to shaping the

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