The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2025

Filed:

Oct. 31, 2023
Applicants:

Michele Quarantelli, Brescia, IT;

Alberto Piadena, Guidizzolo, IT;

Tomasz Brozek, Morgan Hill, CA (US);

Christopher Hess, Belmont, CA (US);

Larg Weiland, Hollister, CA (US);

Sharad Saxena, Richardson, TX (US);

Inventors:

Michele Quarantelli, Brescia, IT;

Alberto Piadena, Guidizzolo, IT;

Tomasz Brozek, Morgan Hill, CA (US);

Christopher Hess, Belmont, CA (US);

Larg Weiland, Hollister, CA (US);

Sharad Saxena, Richardson, TX (US);

Assignee:

PDF Solutions, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2020.01); G01R 19/00 (2006.01); G01R 31/27 (2006.01); G01R 31/28 (2006.01); G01R 31/52 (2020.01); H03K 3/03 (2006.01); H03K 3/354 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2621 (2013.01); G01R 31/275 (2013.01);
Abstract

A novel system for in-product Bias Temperature Instability (BTI) characterization that allows for characterization of transistor degradation rates is disclosed; it is self-testing and can be embedded in real products without impacting the host functionality. The test data collected during product chip testing (at Electrical Wafer Sort) can be used for identification of abnormal material and for material disposition, or to predict the chip aging rate and premature failure risk due to BTI degradation. The system can also collect the data from the real time device aging in the field, during the host chip operational lifetime. The system is equipped with local programmable power supply generation and self-test capabilities to allow concurrent operations with the host application. The Devices Under Test (DUTs) consist of standard cell-based Ring Oscillators (ROs) which have the unique capability of decoupling the BTI effects on N-type and P-type MOSFET transistors. New switching circuitry is implemented that provides for minimal delay between the stress and measurement phases, thus giving the system the capability of fully characterizing the BTI relaxation dynamic.


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