Enter inventor name

Los Altos Hills, CA, United States of America

John Kibarian

This inventor holds 90 USPTO granted patents, primarily in Semiconductor Technology (CPC class H01L27-0207). Top assignee: Pdf Solutions, Incorporated. Active years: 2004-2024.

USPTO Granted Patents = 90

% Patents Active = 8.9

Average Co-Inventor Count = 22.0

ph-index = 10

Forward Citations = 651(Granted Patents)

Forward Citations (Not Self Cited) = 592(Dec 10, 2025)

Inventors with similar research interests:

🔬 See more inventors

Company Filing History:

90 out of 203

Pdf Solutions, Incorporated

patents

Years Active: 2004-2024

Loading Chart...

Areas of Expertise:

Non-Contact Measurements

Integrated Circuits

Fill Cells

NCEM Technology

Semiconductor Wafer

Test Structures

Electrical Measurements

Short Circuit Detection

Standard Cell Compatibility

E-Beam Pads

Process Development

Tip-to-Side Short

90 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12038802 - Collaborative learning model for semiconductor applications (2024-07-16),

2. 11107804 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-31),

3. 11081477 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-03),

4. 11081476 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-03),

5. 11075194 - IC with test structures and E-beam pads embedded within a contiguous standard cell area (2021-07-27),

6. 11018126 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-05-25),

7. 10978438 - IC with test structures and E-beam pads embedded within a contiguous standard cell area (2021-04-13),

8. 10854522 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas (2020-12-01),

9. 10777472 - IC with test structures embedded within a contiguous standard cell area (2020-09-15),

10. 10593604 - Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells (2020-03-17),

11. 10290552 - Methods for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage (2019-05-14),

12. 10269786 - Integrated circuit containing first and second DOEs of standard Cell Compatible, NCEM-enabled Fill Cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including corner short configured fill cells (2019-04-23),

13. 10211112 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas (2019-02-19),

14. 10211111 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side sort, and corner short test areas (2019-02-19),

15. 10199294 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage (2019-02-05),

Title: Innovator Spotlight: John Kibarian

Introduction

John Kibarian, a prominent inventor based in Los Altos Hills, CA, has made significant contributions to the field of semiconductor applications. With an impressive portfolio of 90 patents, Kibarian's work has both advanced technology and enhanced collaborative learning in semiconductor processes.

Latest Patents

Among his recent innovations, Kibarian introduced the "Collaborative Learning Model for Semiconductor Applications," which employs a rule-based model to determine initial wafer classifications. This process is augmented by a machine learning model that predicts wafer classifications. Notably, the system allows multiple users to manually review, confirm, or adjust classifications, feeding all input back into the machine learning model to refine its classification capabilities continuously.

Another noteworthy patent is his development of an "IC with Test Structures and E-Beam Pads Embedded Within a Contiguous Standard Cell Area." This invention comprises an integrated circuit (IC) featuring a standard cell area equipped with a 4x3 e-beam pad, designed to be compatible with advanced manufacturing processes. It also includes an associated e-beam testable structure, enhancing testing efficiency in semiconductor designs.

Career Highlights

Kibarian's career is marked by his role at Pdf Solutions, Incorporated, where his expertise has contributed to advancing semiconductor technologies. His innovative approach has helped establish the company as a leader in providing solutions for semiconductor manufacturing challenges.

Collaborations

Throughout his career, Kibarian has collaborated with esteemed colleagues such as Christopher Hess and Dennis Ciplickas. Their teamwork has been integral in pushing the boundaries of semiconductor technology and fostering advancements that benefit the industry as a whole.

Conclusion

John Kibarian's extensive patent portfolio and innovative contributions in semiconductor applications reflect his expertise and commitment to advancing technology. His work not only enhances industry practices but also paves the way for future developments in collaborative learning and manufacturing processes.

Profile summary based on public USPTO records.

Please report any incorrect information to [email protected]