IDiyas

For the Inventor, By the Inventor

Tokyo, Japan

Nobuharu Yokoyama

USPTO Granted Patents = 82

Average Co-Inventor Count = 26.0

ph-index = 8

Forward Citations = 254(Granted Patents)

DiyaCoin DiyaCoin = 0.03 


Inventors with similar research interests:


Company Filing History:

goldMedal82 out of 203 
 
Pdf Solutions, Incorporated
 patents

Years Active: 2017-2021

where 'Filed Patents' based on already Granted Patents

82 patents (USPTO):
1. 11107804 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-31),
2. 11081477 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-03),
3. 11081476 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-03),
4. 11075194 - IC with test structures and E-beam pads embedded within a contiguous standard cell area (2021-07-27),
5. 11018126 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-05-25),
6. 10978438 - IC with test structures and E-beam pads embedded within a contiguous standard cell area (2021-04-13),
7. 10854522 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas (2020-12-01),
8. 10777472 - IC with test structures embedded within a contiguous standard cell area (2020-09-15),
9. 10593604 - Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells (2020-03-17),
10. 10290552 - Methods for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage (2019-05-14),
11. 10269786 - Integrated circuit containing first and second DOEs of standard Cell Compatible, NCEM-enabled Fill Cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including corner short configured fill cells (2019-04-23),
12. 10211112 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas (2019-02-19),
13. 10211111 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side sort, and corner short test areas (2019-02-19),
14. 10199294 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage (2019-02-05),
15. 10199293 - Method for processing a semiconductor water using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, side to side short, and chamfer short test areas (2019-02-05),

Title: Nobuharu Yokoyama: Innovator in Integrated Circuit Technology

Introduction

Nobuharu Yokoyama, based in Tokyo, Japan, is a distinguished inventor with an impressive portfolio of 82 patents. His contributions to the field of integrated circuits (IC) have significantly impacted the advancements in semiconductor technologies.

Latest Patents

Among his latest innovations are two notable patents focusing on integrated circuits. The first patent outlines an "IC with test structures and e-beam pads embedded within a contiguous standard cell area." This innovation incorporates a contiguous standard cell area designed with a 4x3 e-beam pad, making it compatible with advanced manufacturing processes and featuring an associated e-beam testable structure. This development demonstrates the continual evolution in the IC domain, addressing the growing demands for efficiency and functionality.

Career Highlights

Nobuharu Yokoyama has made remarkable contributions during his tenure at Pdf Solutions, Incorporated. His expertise and innovative mindset have paved the way for new technologies in the semiconductor industry. The vast number of patents he holds is a testament to his creativity and dedication to advancing technology.

Collaborations

Throughout his career, Nobuharu has collaborated with esteemed colleagues like Stephen Lam and Dennis Ciplickas. Working alongside other talented professionals has allowed him to further enhance his innovations and bring transformative solutions to the market.

Conclusion

Nobuharu Yokoyama stands out as a prominent figure in the field of integrated circuit technology. His substantial number of patents and groundbreaking innovations continue to influence the industry, making him a key player in the future of semiconductor advancements.

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