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For the Inventor, By the Inventor

Santa Clara, CA, United States of America

Marci Liao

USPTO Granted Patents = 82

Average Co-Inventor Count = 26.0

ph-index = 8

Forward Citations = 254(Granted Patents)

Forward Citations (Not Self Cited) = 202(Dec 10, 2025)


Inventors with similar research interests:


Company Filing History:

goldMedal82 out of 203 
 
Pdf Solutions, Incorporated
 patents

Years Active: 2017-2021

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Areas of Expertise:
Integrated Circuits
Non-Contact Electrical Measurements
Semiconductor Wafers
NCEM-Enabled Fill Cells
Test Structures
Charged Particle-Beam Inspection
Tip-to-Side Shorts
Via Open Configured Fill Cells
Corner Short Configured Fill Cells
Chamfer Short Configured Fill Cells
Standard Cell Compatibility
82 patents (USPTO):Explore Patents
1. 11107804 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-31),
2. 11081477 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-03),
3. 11081476 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-03),
4. 11075194 - IC with test structures and E-beam pads embedded within a contiguous standard cell area (2021-07-27),
5. 11018126 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-05-25),
6. 10978438 - IC with test structures and E-beam pads embedded within a contiguous standard cell area (2021-04-13),
7. 10854522 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas (2020-12-01),
8. 10777472 - IC with test structures embedded within a contiguous standard cell area (2020-09-15),
9. 10593604 - Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells (2020-03-17),
10. 10290552 - Methods for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage (2019-05-14),
11. 10269786 - Integrated circuit containing first and second DOEs of standard Cell Compatible, NCEM-enabled Fill Cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including corner short configured fill cells (2019-04-23),
12. 10211112 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas (2019-02-19),
13. 10211111 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side sort, and corner short test areas (2019-02-19),
14. 10199294 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage (2019-02-05),
15. 10199293 - Method for processing a semiconductor water using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, side to side short, and chamfer short test areas (2019-02-05),

Title: Marci Liao: A Pioneer in Integrated Circuit Innovations

Introduction: Marci Liao, based in Santa Clara, CA, is a distinguished inventor with an impressive portfolio of 82 patents. His contributions to the field of integrated circuits (ICs) reflect significant advancements in manufacturing processes and testing methodologies.

Latest Patents: Among his latest inventions is a groundbreaking IC that features test structures and electron beam (e-beam) pads embedded within a contiguous standard cell area. This innovative design includes a 4x3 e-beam pad that is compatible with advanced manufacturing processes, paired with an associated e-beam testable structure. This development enhances the usability and efficiency of integrated circuits in various applications.

Career Highlights: Marci Liao has made substantial contributions during his career at Pdf Solutions, Incorporated. His work has not only propelled the company's innovation in the IC sector but has set new industry standards for performance and reliability.

Collaborations: Throughout his career, Marci has collaborated with notable colleagues such as Stephen Lam and Dennis Ciplickas. Together, they have driven numerous projects aimed at advancing the capabilities of integrated circuit technology, reinforcing the importance of teamwork and interdisciplinary collaboration in the innovation process.

Conclusion: Marci Liao is a pivotal figure in the realm of integrated circuit innovation. With a wealth of patents and collaborative efforts, he continues to shape the future of technology, contributing to more efficient and advanced integrated circuit designs for various applications. His work symbolizes the dedication and ingenuity that define successful inventors in today's fast-paced technological landscape.

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