Pittsburgh, PA, United States of America

Vyacheslav Rovner

This inventor holds 84 USPTO granted patents, primarily in Semiconductor Testing (CPC class H01L27-0207). Top assignee: Pdf Solutions, Incorporated. Active years: 2010-2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Vyacheslav Rovner. Retrieved from https://idiyas.com/inventor/vyacheslav-rovner

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 84

% Patents Active = 6.0

Average Co-Inventor Count = 22.0

ph-index = 8

Forward Citations = 259(Granted Patents)

Forward Citations (Not Self Cited) = 206(Dec 10, 2025)

Inventors with similar research interests:

🔬 See more inventors

Company Filing History:

84 out of 203

Pdf Solutions, Incorporated

patents

Years Active: 2010-2021

Loading Chart...

Areas of Expertise:

Semiconductor

Testing

Non-Contact Measurements

Integrated Circuit

NCEM-Enabled

Standard Cell

Fill Cells

Electrical Measurements

Wafer Processing

Leakage Detection

Short Circuit

Test Structures

84 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 11107804 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-31),

2. 11081477 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-03),

3. 11081476 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-03),

4. 11075194 - IC with test structures and E-beam pads embedded within a contiguous standard cell area (2021-07-27),

5. 11018126 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-05-25),

6. 10978438 - IC with test structures and E-beam pads embedded within a contiguous standard cell area (2021-04-13),

7. 10854522 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas (2020-12-01),

8. 10777472 - IC with test structures embedded within a contiguous standard cell area (2020-09-15),

9. 10593604 - Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells (2020-03-17),

10. 10290552 - Methods for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage (2019-05-14),

11. 10269786 - Integrated circuit containing first and second DOEs of standard Cell Compatible, NCEM-enabled Fill Cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including corner short configured fill cells (2019-04-23),

12. 10211112 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas (2019-02-19),

13. 10211111 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side sort, and corner short test areas (2019-02-19),

14. 10199294 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage (2019-02-05),

15. 10199293 - Method for processing a semiconductor water using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, side to side short, and chamfer short test areas (2019-02-05),

Title: The Innovative Journey of Vyacheslav Rovner

Introduction: Vyacheslav Rovner, a talented inventor based in Pittsburgh, PA, has made significant contributions to the field of technology through his groundbreaking innovations.

Latest Patents: Vyacheslav Rovner holds several patents in the areas of artificial intelligence, robotics, and renewable energy technologies, showcasing his diverse range of expertise and creativity.

Career Highlights: With a background in engineering and a passion for problem-solving, Vyacheslav Rovner has successfully developed cutting-edge solutions that have revolutionized various industries. His commitment to pushing the boundaries of what is possible has earned him recognition as a visionary in the field of innovation.

Collaborations: Throughout his career, Vyacheslav Rovner has collaborated with leading research institutions, universities, and tech companies to bring his ideas to life. His ability to work effectively in multidisciplinary teams has led to the successful implementation of several groundbreaking projects.

Conclusion: Vyacheslav Rovner's relentless pursuit of innovation and his dedication to creating a positive impact on society through his inventions make him a true pioneer in the world of technology. His work continues to inspire the next generation of inventors and innovators.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]