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For the Inventor, By the Inventor

New Galilee, PA, United States of America

Timothy Fiscus

USPTO Granted Patents = 82

Average Co-Inventor Count = 26.0

ph-index = 8

Forward Citations = 254(Granted Patents)

DiyaCoin DiyaCoin = 0.03 


Inventors with similar research interests:


Company Filing History:

goldMedal82 out of 203 
 
Pdf Solutions, Incorporated
 patents

Years Active: 2017-2021

where 'Filed Patents' based on already Granted Patents

82 patents (USPTO):
1. 11107804 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-31),
2. 11081477 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-03),
3. 11081476 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-03),
4. 11075194 - IC with test structures and E-beam pads embedded within a contiguous standard cell area (2021-07-27),
5. 11018126 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-05-25),
6. 10978438 - IC with test structures and E-beam pads embedded within a contiguous standard cell area (2021-04-13),
7. 10854522 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas (2020-12-01),
8. 10777472 - IC with test structures embedded within a contiguous standard cell area (2020-09-15),
9. 10593604 - Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells (2020-03-17),
10. 10290552 - Methods for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage (2019-05-14),
11. 10269786 - Integrated circuit containing first and second DOEs of standard Cell Compatible, NCEM-enabled Fill Cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including corner short configured fill cells (2019-04-23),
12. 10211112 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas (2019-02-19),
13. 10211111 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side sort, and corner short test areas (2019-02-19),
14. 10199294 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage (2019-02-05),
15. 10199293 - Method for processing a semiconductor water using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, side to side short, and chamfer short test areas (2019-02-05),

Title: The Innovations of Timothy Fiscus

Introduction: Timothy Fiscus is a renowned inventor based in New Galilee, Pennsylvania, holding an impressive portfolio of 82 patents. His contributions to the field of integrated circuits (IC) and advanced manufacturing processes have significantly influenced technological advancements.

Latest Patents: Among his latest innovations are groundbreaking patents for integrated circuits featuring test structures and e-beam pads embedded within a contiguous standard cell area. These ICs include a 4x3 e-beam pad that is compatible with advanced manufacturing processes, enabling an associated e-beam testable structure that enhances testing efficiency and accuracy.

Career Highlights: Timothy has made significant strides in the field while working at Pdf Solutions, Incorporated. His expertise in integrated circuit design and testing has positioned him as a key contributor to advancements within the industry. His dedication to innovation continues to drive improvements in manufacturing processes and IC technology.

Collaborations: Throughout his career, Timothy has collaborated with prominent professionals such as Stephen Lam and Dennis Ciplickas. These partnerships underline his ability to work alongside other talented individuals, fostering an environment of creativity and shared knowledge that propels innovation forward.

Conclusion: Timothy Fiscus's extensive array of patents and innovative work in integrated circuits illustrate his impact on the technological landscape. His continued efforts in collaboration and invention ensure that he remains a pivotal figure in the realm of innovations and inventions.

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