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For the Inventor, By the Inventor

Pittsburgh, PA, United States of America

Andrzej Strojwas

USPTO Granted Patents = 84

Average Co-Inventor Count = 22.0

ph-index = 9

Forward Citations = 458(Granted Patents)

DiyaCoin DiyaCoin = 0.08 


Inventors with similar research interests:


Location History:

  • Pitssburgh, PA (US) (2017)
  • Pittsburgh, PA (US) (2007 - 2021)

Company Filing History:

goldMedal84 out of 203 
 
Pdf Solutions, Incorporated
 patents

Years Active: 2007-2021

where 'Filed Patents' based on already Granted Patents

84 patents (USPTO):
1. 11107804 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-31),
2. 11081477 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-03),
3. 11081476 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-03),
4. 11075194 - IC with test structures and E-beam pads embedded within a contiguous standard cell area (2021-07-27),
5. 11018126 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-05-25),
6. 10978438 - IC with test structures and E-beam pads embedded within a contiguous standard cell area (2021-04-13),
7. 10854522 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas (2020-12-01),
8. 10777472 - IC with test structures embedded within a contiguous standard cell area (2020-09-15),
9. 10593604 - Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells (2020-03-17),
10. 10290552 - Methods for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage (2019-05-14),
11. 10269786 - Integrated circuit containing first and second DOEs of standard Cell Compatible, NCEM-enabled Fill Cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including corner short configured fill cells (2019-04-23),
12. 10211112 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas (2019-02-19),
13. 10211111 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side sort, and corner short test areas (2019-02-19),
14. 10199294 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-side short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage (2019-02-05),
15. 10199293 - Method for processing a semiconductor water using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, side to side short, and chamfer short test areas (2019-02-05),

As an AI assistant specializing in innovations, inventions, inventors, patent attorneys, assignees, and patents, I can provide you with an article about inventor Andrzej Strojwas. Here it is:

Title: The Innovative Journey of Andrzej Strojwas

Introduction:

Andrzej Strojwas is a prolific inventor based in Pittsburgh, PA, with an impressive portfolio of 84 patents to his name. His contributions to the field of integrated circuits have been groundbreaking, with a focus on advancing manufacturing processes for greater efficiency and reliability.

Latest Patents:

Strojwas' latest patents include an Integrated Circuit (IC) featuring test structures and e-beam pads embedded within a contiguous standard cell area. This innovation allows for enhanced compatibility with advanced manufacturing techniques, showcasing his commitment to pushing the boundaries of technological possibilities.

Career Highlights:

Currently affiliated with Pdf Solutions, Incorporated, Strojwas continues to shape the future of semiconductor technology. His expertise in standard cell design and e-beam testing has earned him recognition as a key player in the industry, driving forward progress with each new invention.

Collaborations:

Strojwas has collaborated with esteemed colleagues such as Stephen Lam and Dennis Ciplickas, further enriching his work with diverse perspectives and collective expertise. These partnerships have undoubtedly contributed to the success of his innovative projects and the impact they have had on the field.

Conclusion:

In conclusion, Andrzej Strojwas stands as a beacon of innovation in the realm of integrated circuits, with a remarkable track record of patents that reflect his dedication to advancing technology. His work not only exemplifies excellence in the field but also inspires future generations of inventors to continue pushing the boundaries of what is possible in the ever-evolving landscape of semiconductor technologies.

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