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For the Inventor, By the Inventor

Pittsburgh, PA, United States of America

Jonathan Haigh

This inventor holds 95 USPTO granted patents and 1 published patent application, primarily in Semiconductor Processing (CPC class H01L27-0207). Top assignee: Pdf Solutions, Incorporated. Active years: 2015-2021.

USPTO Granted Patents = 95 

% Patents Active = 8.4

Average Co-Inventor Count = 7.2

ph-index = 9

Forward Citations = 300(Granted Patents)

Forward Citations (Not Self Cited) = 237(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • San Jose, CA (US) (2017 - 2020)
  • Pittsburgh, PA (US) (2015 - 2021)

Company Filing History:

goldMedal95 out of 203 
 
Pdf Solutions, Incorporated
 patents

Years Active: 2015-2021

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Areas of Expertise:
Semiconductor Wafer
Non-Contact Measurements
Integrated Circuits
Test Structures
NCEM-Enabled Fill Cells
Standard Logic Cells
Electrical Measurements
Short or Leakage
Design Rules
Charged Particle-Beam Inspector
Fill Cell Configurations
DOEs
95 patents (USPTO):Explore Patents
1. 11107804 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-31),
2. 11081477 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-03),
3. 11081476 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-08-03),
4. 11075194 - IC with test structures and E-beam pads embedded within a contiguous standard cell area (2021-07-27),
5. 11018126 - IC with test structures and e-beam pads embedded within a contiguous standard cell area (2021-05-25),
6. 10978438 - IC with test structures and E-beam pads embedded within a contiguous standard cell area (2021-04-13),
7. 10854522 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas (2020-12-01),
8. 10803221 - Snap-to valid pattern system and method (2020-10-13),
9. 10777472 - IC with test structures embedded within a contiguous standard cell area (2020-09-15),
10. 10622344 - IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a substantially uniform variant of the original set of design rules and methods for making the same (2020-04-14),
11. 10593604 - Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells (2020-03-17),
12. 10290552 - Methods for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage (2019-05-14),
13. 10269786 - Integrated circuit containing first and second DOEs of standard Cell Compatible, NCEM-enabled Fill Cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including corner short configured fill cells (2019-04-23),
14. 10263011 - Process for making ICs from standard logic cells that utilize TS cut mask(s) and avoid DFM problems caused by closely spaced gate contacts and TSCUT jogs (2019-04-16),
15. 10211112 - Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and side-to-side short test areas (2019-02-19),

Title: The Innovative Mind of Jonathan Haigh: Revolutionizing IC Technology

Introduction: Jonathan Haigh, a prolific inventor based in Pittsburgh, PA, holds an impressive portfolio of 95 patents in the field of integrated circuits (IC). His groundbreaking work at Pdf Solutions, Incorporated, has propelled him to the forefront of advanced manufacturing processes.

Latest Patents: Among his latest patents is an IC design featuring test structures and e-beam pads embedded within a contiguous standard cell area. This innovative approach showcases Haigh's dedication to enhancing efficiency and compatibility in IC fabrication.

Career Highlights: With a keen focus on pushing the boundaries of IC technology, Jonathan Haigh has consistently delivered cutting-edge solutions that have redefined the industry's standards. His wealth of experience and expertise have solidified his reputation as a trailblazer in the field.

Collaborations: Haigh's collaborative spirit is evident in his work alongside accomplished peers such as Vyacheslav Rovner and Stephen Lam. Together, they have synergized their talents to drive innovation and shape the future of IC design.

Conclusion: Jonathan Haigh's remarkable journey as an inventor underscores his unwavering commitment to pushing the limits of technological advancement in the realm of ICs. His relentless pursuit of excellence continues to inspire and elevate the field, making him a true visionary in the world of innovation.

Profile summary based on public USPTO records.
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