Pdf Solutions, Incorporated

Jonathan Haigh

Vyacheslav Rovner

Indranil De

Jeremy Cheng

Christopher Hess

Dennis Ciplickas

Larg H Weiland

Sherry F Lee

John Kibarian

Kimon Michaels

Tomasz Brozek

Hans Eisenmann

Sheng-Che Lin

Rakesh Vallishayee

Stephen Lam

Andrzej Strojwas

Markus Rauscher

Carl Taylor

Kelvin Doong

Conor O'Sullivan

Timothy Fiscus

Marcin Strojwas

Nobuharu Yokoyama

Simone Comensoli

Marci Liao

Hideki Matsuhashi

Matthew Moe

Elizabeth Lagnese

An IC that includes a contiguous standard cell area with a 4x3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

IC with test structures and e-beam pads embedded within a contiguous standard cell area

An IC that includes a contiguous standard cell area with a 4&#xd7;3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

IC with test structures and E-beam pads embedded within a contiguous standard cell area

A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas.

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas

Described is a method for implementing a snap to capability that enables the manufactured of a valid pattern in a semiconductor device, based upon an originally invalid pattern.

Snap-to valid pattern system and method

An IC includes a contiguous standard cell area with first, second, and third TS-GATE-short-configured test area geometries disposed therein. In some embodiments, the contiguous standard cell area may further include: fourth and fifth TS-GATE-short-configured test area geometries, and/or other test area geometries, such as tip-to-tip-short, tip-to-side-short, diagonal-short, corner-short, interlayer-overlap-short, via-chamfer-short, merged-via-short, snake-open, stitch-open, via-open, or metal-island-open.

IC with test structures embedded within a contiguous standard cell area

The present invention relates to IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a variant of the original set of design rules and methods for making the same.

IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a substantially uniform variant of the original set of design rules and methods for making the same

Improved processes for manufacturing wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements ('NCEM') of fill cells that contain structures configured target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such processes may involve evaluating Designs of Experiments ('DOEs'), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).

Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells

A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with a moving stage and beam deflection to account for motion of the stage.

Methods for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage

An IC includes first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements ('NCEM'). The first DOE contains fill cells configured to enable non-contact (NC) detection of tip-to-side shorts, and the second DOE contains fill cells configured to enable NC detection of corner shorts.

Integrated circuit containing first and second DOEs of standard Cell Compatible, NCEM-enabled Fill Cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including corner short configured fill cells

An improved standard cell chip, library and/or process ensures that there is adequate spacing between TSCUT jogs and nearby gate contacts to avoid inadvertent shorts/leakages that can degrade manufacturing yield or performance.

Process for making ICs from standard logic cells that utilize TS cut mask(s) and avoid DFM problems caused by closely spaced gate contacts and TSCUT jogs

A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side short, and corner short test areas.

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with respective tip-to-tip short, tip-to-side sort, and corner short test areas

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Pittsburgh, PA, United States of America

Jonathan Haigh