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For the Inventor, By the Inventor

Tokyo, Japan

Mitsuaki Katagiri

This inventor holds 63 USPTO granted patents and 11 published patent applications, primarily in Semiconductor Packaging (CPC class H01L). Top assignees: Elpida Memory, Inc., Renesas Technology Corp., Hitachi, Ltd.. Active years: 1999-2023.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Mitsuaki Katagiri. Retrieved from https://idiyas.com/inventor/mitsuaki-katagiri

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 63 

% Patents Active = 58.7

Average Co-Inventor Count = 3.6

ph-index = 12

Forward Citations = 500(Granted Patents)

Forward Citations (Not Self Cited) = 491(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Higashimurayama, JP (1999)
  • Koganei, JP (2001)
  • Nishitokyo, JP (2004 - 2010)
  • Chuo-ku, JP (2009 - 2014)
  • Tokyo Nishitokyo, JP (2018 - 2019)
  • Tokyo, JP (2006 - 2023)

Company Filing History:

goldMedal35 out of 1,458 
 
Elpida Memory, Inc.
 patents
silverMedal8 out of 3,781 
 
Renesas Technology Corp.
 patents
bronzeMedal7 out of 42,743 
 
Hitachi, Ltd.
 patents
4. 7 out of 377 
 
Ps4 Luxco S.a.r.l.
 patents
5. 5 out of 39,294 
 
Micron Technology Incorporated
 patents
6. 1 out of 3 
 
Elipida Memory, Inc.
 patents
7. 1 out of 1 
 
Hitachi, Ltd., Intellectual Property Group
 patent
8. 1 out of 52 
 
Longitude Semiconductor S.a.r.l.
 patents
9. 1 out of 36,735 
 
Nec Corporation
 patents
10. 1 out of 30 
 
Renesas Eastern Japan Semiconductor, Inc.
 patents
11. 3 out of 834,601 
Other
 patents
where one patent can have more than one assignee

Years Active: 1999-2023

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Areas of Expertise:
Stacked Die Package
Face-to-Face Arrangement
Reduced Loop Inductance
Bonding Layer
Wire Retaining Member
Multichip Package
Power Supply Plane
Ground Plane
Dummy Bump
Fine Pitch Grid Array
Solder Joint
Inductance Analysis
63 patents (USPTO):Explore Patents
1. 11705432 - Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding, and related methods and devices (2023-07-18),
2. 11081468 - Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding and related methods, devices and apparatuses (2021-08-03),
3. 10600762 - Apparatuses comprising semiconductor dies in face-to-face arrangements (2020-03-24),
4. 10431566 - Apparatuses comprising semiconductor dies in face-to-face arrangements (2019-10-01),
5. 10115709 - Apparatuses comprising semiconductor dies in face-to-face arrangements (2018-10-30),
6. 9595489 - Semiconductor package with bonding wires of reduced loop inductance (2017-03-14),
7. 9589921 - Semiconductor device (2017-03-07),
8. 9418967 - Semiconductor device (2016-08-16),
9. 9048221 - Device having electrodes formed from bumps with different diameters (2015-06-02),
10. 8970052 - Semiconductor device stack with bonding layer and wire retaining member (2015-03-03),
11. 8941237 - Semiconductor device (2015-01-27),
12. 8853822 - Semiconductor device (2014-10-07),
13. 8796077 - Semiconductor device (2014-08-05),
14. 8680881 - Test method and interposer used therefor (2014-03-25),
15. 8633596 - Semiconductor package with bonding wires of reduced loop inductance (2014-01-21),

Title: The Innovative Journey of Mitsuaki Katagiri

Introduction: Mitsuaki Katagiri is a renowned inventor hailing from Tokyo, Japan, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Mitsuaki Katagiri holds several patents in the areas of robotics, artificial intelligence, and renewable energy technologies, showcasing his continuous commitment to pushing the boundaries of technological advancement.

Career Highlights: With a career spanning over two decades, Katagiri has worked with leading tech companies in Japan, spearheading research and development projects that have led to significant advancements in various industries.

Collaborations: Throughout his career, Mitsuaki Katagiri has collaborated with top researchers, engineers, and scientists both locally and internationally, fostering a culture of innovation and knowledge sharing.

Conclusion: Mitsuaki Katagiri's relentless pursuit of innovation and his passion for creating solutions to complex technological challenges have solidified his position as a pioneering inventor in the global tech landscape.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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