For the Inventor, By the Inventor

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Boise, ID, United States of America

Micron Technology Incorporated

USPTO Granted Patents = 39,222

% Expired Patents = 12.7

CIPO Patents = 2

EPO Patents = 1,042

Trademarks = 17

Forward Citations = 446,659

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6,140 inventors (with patents filed for the assignee):

Gurtej S Sandhu (1,385 out of 1,439 patents)

Leonard Forbes (1,068 out of 1,110 patents)

Warren M Farnworth (754 out of 777 patents)

4. Salman Akram (697 out of 726 patents)

5. Kie Y Ahn (586 out of 613 patents)

6. Frankie F Roohparvar (475 out of 512 patents)

7. Durai Vishak Nirmal Ramaswamy (392 out of 398 patents)

8. Alan G Wood (388 out of 397 patents)

9. Kishore Kumar Muchherla (371 out of 372 patents)

10. David R Hembree (359 out of 365 patents)

11. Trung Tri Doan (354 out of 434 patents)

12. Brent Keeth (316 out of 335 patents)

13. Troy A Manning (308 out of 323 patents)

14. Fernando N Gonzalez (301 out of 310 patents)

15. Sanh D Tang (299 out of 307 patents)

Core Competencies:

Memory Management

Error Correction Code

Data Retention

Fault Tolerance

Non-Volatile Memory

Semiconductor Devices

Memory Arrays

Temperature Compensation

Data Mapping

Thread Management

Cache Optimization

Power Management

39,222 patents: Sort by Forward Citations

1. 12765364 - Tier recess method (2026-10-13),

2. 12765344 - Methods for forming conductive vias, and associated devices and systems (2026-10-13),

3. 12765009 - Semiconductor structure with curved surfaces (2026-10-13),

4. 12764963 - Methods of forming microelectronic devices (2026-10-13),

5. 12764939 - Bit lines having high electrical conductivity and low mutual capacitance and related apparatuses, computing systems, and methods (2026-10-13),

6. 12764928 - Hybrid gate dielectric access device for vertical three-dimensional memory (2026-10-13),

7. 12764875 - Damper for a printed circuit board assembly (2026-10-13),

8. 12764199 - Network storage services implemented via storage products and external software (2026-10-13),

9. 12764101 - Subscription sharing among a group of endpoints having memory devices secured for reliable identity validation (2026-10-13),

10. 12763975 - Endorsed device certificate chain autonomous extension (2026-10-13),

11. 12763931 - Cloud storage with enhanced data privacy (2026-10-13),

12. 12763680 - Voltage domain based error management (2026-10-13),

13. 12763149 - Logical block construction for physical blocks comprising multiple erase blocks coupled to a same string (2026-10-13),

14. 12763133 - Memory die and logic die with wafer-on-wafer bond (2026-10-13),

15. 12763128 - Apparatuses and methods for a per-DRAM addressability synchronizer circuit (2026-10-13),

Company Overview

Micron Technology Incorporated, headquartered in Boise, Idaho, is a leading developer and manufacturer of memory systems. The company specializes in advanced semiconductor devices, focusing on various core technologies such as memory management, error correction code, and non-volatile memory. Micron's innovations in memory arrays and fault tolerance contribute significantly to data retention and temperature compensation, making it a pivotal player in the global semiconductor industry.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 13 2026

39,222 Patents

#1 in Boise, ID

#1 in Idaho

#7 in US

#16 in the World

Boise, ID, United States of America

Micron Technology Incorporated

Forward Citations = 446,659

6,140 inventors:

Gurtej S Sandhu (1,385 out of 1,439 patents)

Leonard Forbes (1,068 out of 1,110 patents)

Warren M Farnworth (754 out of 777 patents)

4. Salman Akram (697 out of 726 patents)

5. Kie Y Ahn (586 out of 613 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Micron Technology Incorporated. Retrieved from https://idiyas.com/company/micron-technology

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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