The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2015

Filed:

Oct. 09, 2013
Applicant:

Ps4 Luxco S.a.r.l., Luxembourg, LU;

Inventors:

Yu Hasegawa, Tokyo, JP;

Mitsuaki Katagiri, Tokyo, JP;

Satoshi Isa, Tokyo, JP;

Ken Iwakura, Tokyo, JP;

Dai Sasaki, Tokyo, JP;

Assignee:

PS4 Luxco S.a.r.l., Luxembourg, LU;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 24/45 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/45015 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48095 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48471 (2013.01); H01L 2224/48479 (2013.01); H01L 2224/48599 (2013.01); H01L 2224/4899 (2013.01); H01L 2224/49171 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/85007 (2013.01); H01L 2224/85051 (2013.01); H01L 2225/0651 (2013.01); H01L 2924/01004 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01014 (2013.01); H01L 2924/01057 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/014 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/20755 (2013.01); H01L 2924/30105 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01033 (2013.01); H01L 2224/48465 (2013.01); H01L 2924/12041 (2013.01);
Abstract

In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip.


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