The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 2015
Filed:
Jun. 18, 2013
Applicant:
Elpida Memory, Inc., Tokyo, JP;
Inventors:
Yu Hasegawa, Tokyo, JP;
Mitsuaki Katagiri, Tokyo, JP;
Assignee:
PS4 Luxco S.A.R.L., Luxembourg, LU;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 23/13 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49811 (2013.01); H01L 23/13 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 24/83 (2013.01); H01L 24/85 (2013.01); H01L 24/97 (2013.01); H01L 25/0657 (2013.01); H01L 23/538 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/4813 (2013.01); H01L 2224/4824 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/48471 (2013.01); H01L 2224/48479 (2013.01); H01L 2224/4911 (2013.01); H01L 2224/49175 (2013.01); H01L 2224/49426 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/78301 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/85051 (2013.01); H01L 2224/85186 (2013.01); H01L 2224/92147 (2013.01); H01L 2224/97 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06558 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/014 (2013.01); H01L 2924/15311 (2013.01); H01L 2224/2919 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/0665 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48227 (2013.01); H01L 24/78 (2013.01);
Abstract
A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad.