The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 2021

Filed:

Aug. 28, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Hiroki Fujisawa, Kanagawa, JP;

Raj K. Bansal, Taichung, TW;

Shunji Kuwahara, Tokyo, JP;

Mitsuaki Katagiri, Tokyo, JP;

Satoshi Isa, Tokyo, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 25/18 (2006.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01); G11C 11/4096 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); G11C 11/4096 (2013.01); H01L 24/07 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/0233 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/02375 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48225 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06558 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06565 (2013.01);
Abstract

Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.


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