Elpida Memory, Inc.

Renesas Technology Corp.

Hitachi, Ltd.

Ps4 Luxco S.a.r.l.

Micron Technology Incorporated

Other

Nec Corporation

Longitude Semiconductor S.a.r.l.

Renesas Eastern Japan Semiconductor, Inc.

Elipida Memory, Inc.

Hitachi, Ltd., Intellectual Property Group

Mitsuaki Katagiri

Satoshi Isa

Dai Sasaki

Hisashi Tanie

Ichiro Anjo

Fumiyuki Osanai

Yu Hasegawa

Hiromasa Takeda

Ken Iwakura

Yuji Shirai

Hiroki Fujisawa

Yutaka Uematsu

Takashi Suga

Hiroya Shimizu

Yukitoshi Hirose

Satoshi Itaya

Kazutaka Koshiishi

Asao Nishimura

Yuji Watanabe

Satoshi Nakamura

Yoji Nishio

Hideki Osaka

Seiji Narui

Atsushi Hiraishi

Yoshihide Yamaguchi

Toshio Miyamoto

Shotaro Kobayashi

Hiroshi Moriya

Shigeru Takahashi

Yoshiyuki Kado

Raj K Bansal

Shunji Kuwahara

Koji Hosokawa

Tadayasu Miki

Shigeo Ogasawara

Noriaki Oka

Jun Kayamori

Hiroaki Ikeda

Tomonori Sekiguchi

Kazumasa Yanagisawa

Kunihiko Nishi

Kunihiro Tsubosaki

Masachika Masuda

Hiroshi Ikeda

Hiroyuki Ohta

Yasushi Takahashi

Hideaki Takahashi

Osamu Nagashima

Seiji Funaba

Tatsuya Nagata

Kyoichi Nagata

Tatemi Ido

Satoshi Muraoka

Shuji Kikuchi

Shigeyuki Nakazawa

Nae Hisano

Katsunori Hirano

Masami Usami

Satoru Konishi

Kenji Ujiie

Masaharu Imazato

Kensuke Tsuneda

Toru Chonan

Kenji Nishimoto

Takehiro Ohnishi

Yuji Sonoda

Go Shinkai

Haruo Akahoshi

Takashi Iida

Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.

Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding, and related methods and devices

Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding and related methods, devices and apparatuses

Some embodiments include an apparatus having a first chip and a second chip. Each of the first and second chips comprises a multilevel wiring structure and a redistribution wiring layer over the multilevel wiring structure. The redistribution wiring layers include redistribution wiring and pads electrically coupled to the redistribution wiring. The first chip is mounted above the second chip so that the redistribution wiring layer of the first chip faces the redistribution wiring layer of the second chip. The pad of the first chip faces the pad of the second chip, and is vertically spaced from the pad of the second chip by an intervening insulative region. The redistribution wiring of the second chip is electrically coupled to the redistribution wiring of the first chip through a bonding region.

Apparatuses comprising semiconductor dies in face-to-face arrangements

A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers.

Semiconductor package with bonding wires of reduced loop inductance

In one semiconductor device, a semiconductor chip has first and second pad electrodes disposed on the main surface thereof, insulating films that cover the main surface of the semiconductor chip, a rewiring layer that is disposed between the insulating films, and a plurality of external terminals disposed on the top of the insulating film. The plane size of the first pad electrode and the second pad electrode differ from one another, and the first pad electrode and the second pad electrode are connected to any of the plurality of external terminals via the rewiring layer.

Semiconductor device

A semiconductor device includes a package substrate, an IF chip, and a core chip. The package substrate has: first electrodes aligned and disposed on a first rear surface; second electrodes aligned and disposed in the first direction (Y direction) on a first front surface; and wiring that electrically connects the first electrodes and the second electrodes. The IF chip has third electrodes bonded to the second electrodes. The core chip is connected to the IF chip. In the first direction, the length of the IF chip is more than that of the core chip but equal to or less than that of the package substrate. One of the first electrodes is disposed further toward the outside than a core chip end portion in the first direction. At least one of the second electrodes is disposed further toward the outside than the core chip end portion in the first direction.

A device has a first substrate having a first surface; a first electrode pad arranged on the first surface of the first substrate; a first insulator film provided on the first surface of the first substrate so that the first electrode pad is exposed; a first bump electrode provided on the first electrode pad and having a first diameter; and a second bump electrode provided on the first insulator film and having a second diameter smaller than the first diameter.

Device having electrodes formed from bumps with different diameters

In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip.

Semiconductor device stack with bonding layer and wire retaining member

A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad.

A semiconductor device according to this invention includes a first power line that supplies power to a first circuit, a second power line that supplies power to a second circuit, and a capacitive element that is provided between the first power line and the second power line.

Provided is a semiconductor device with a semiconductor chip mounted on a small-sized package substrate that includes a slot, a large number of external connection terminals, and bonding fingers. The bonding fingers are connected to the external connection terminals. The bonding fingers constitute a bonding finger arrangement in a central section and end sections of a bonding finger area along each longer side of the slot. The arrangement includes a first bonding finger array, which is located at a close distance from each longer side of the slot, and a second array, which is located at a farther distance than the distance of the first bonding finger array from each longer side of the slot. The central section of the bonding finger area includes the second bonding finger array, and the end sections of the bonding finger area include the first bonding finger array.

An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.

Test method and interposer used therefor

Growing community of inventors

Tokyo, Japan

Mitsuaki Katagiri