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For the Inventor, By the Inventor

San Jose, CA, United States of America

Henry Chien

This inventor holds 76 USPTO granted patents and 1 published patent application and 6 EPO patents, primarily in 3D Memory Technology (CPC class H01L). Top assignees: Sandisk Technologies Inc., Sandisk Corporation, Sandisk 3D LLC. Active years: 1996-2018.

USPTO Granted Patents = 76 

% Patents Active = 69.7


Average Co-Inventor Count = 4.6

ph-index = 28

Forward Citations = 2,508(Granted Patents)

Forward Citations (Not Self Cited) = 2,371(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Manassas, VA (US) (2005 - 2007)
  • Milpitas, CA (US) (2017)
  • San Jose, CA (US) (1996 - 2018)

Company Filing History:

goldMedal49 out of 4,943 
 
Sandisk Technologies Inc.
 patents
silverMedal21 out of 1,339 
 
Sandisk Corporation
 patents
bronzeMedal6 out of 669 
 
Sandisk 3D LLC
 patents

Years Active: 1996-2018

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Areas of Expertise:
3D Memory
Vertical NAND
Multilevel Memory
Non-Volatile Memory
Memory Stack
Conductive Layers
Floating Gates
Resistance-Switching
Cavity Fill Material
High Stack Memory
Electrical Isolation
Memory Fabrication
76 patents (USPTO):Explore Patents
1. 9870945 - Crystalline layer stack for forming conductive layers in a three-dimensional memory structure (2018-01-16),
2. 9853043 - Method of making a multilevel memory stack structure using a cavity containing a sacrificial fill material (2017-12-26),
3. 9728551 - Multi-tier replacement memory stack structure integration scheme (2017-08-08),
4. 9728546 - 3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same (2017-08-08),
5. 9716101 - Forming 3D memory cells after word line replacement (2017-07-25),
6. 9698149 - Non-volatile memory with flat cell structures and air gap isolation (2017-07-04),
7. 9672917 - Stacked vertical memory array architectures, systems and methods (2017-06-06),
8. 9666590 - High stack 3D memory and method of making (2017-05-30),
9. 9659956 - Three-dimensional memory device containing source select gate electrodes with enhanced electrical isolation (2017-05-23),
10. 9620514 - 3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same (2017-04-11),
11. 9583500 - Multilevel memory stack structure and methods of manufacturing the same (2017-02-28),
12. 9530790 - Three-dimensional memory device containing CMOS devices over memory stack structures (2016-12-27),
13. 9530785 - Three-dimensional memory devices having a single layer channel and methods of making thereof (2016-12-27),
14. 9524976 - Method of integrating select gate source and memory hole for three-dimensional non-volatile memory device (2016-12-20),
15. 9524779 - Three dimensional vertical NAND device with floating gates (2016-12-20),

Title: Top Inventor in San Jose

Introduction: Shan Liu is recognized as a leading inventor in San Jose, contributing significantly to various technological advancements.

Latest Patents: Shan Liu holds several patents that showcase innovative solutions in his field.

Career Highlights: Throughout his career, Liu has achieved numerous milestones that highlight his expertise and impact on technology.

Collaborations: He has worked with various organizations and teams, fostering collaboration to drive innovation.

Conclusion: Shan Liu's contributions continue to shape the landscape of technology in San Jose and beyond.

Profile summary based on public USPTO records.
Please report any incorrect information to [email protected]
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