The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 25, 2017
Filed:
Oct. 30, 2015
Sandisk Technologies Inc., Plano, TX (US);
Zhenyu Lu, Milpitas, CA (US);
Hiro Kinoshita, Milpitas, CA (US);
Daxin Mao, Milpitas, CA (US);
Johann Alsmeier, San Jose, CA (US);
Wenguang Shi, Milpitas, CA (US);
Yingda Dong, San Jose, CA (US);
Henry Chien, Milpitas, CA (US);
Kensuke Yamaguchi, Milpitas, CA (US);
Xiaolong Hu, Yokkaichi, JP;
SanDisk Technologies LLC, Plano, TX (US);
Abstract
Techniques for forming 3D memory arrays are disclosed. Memory openings are filled with a sacrificial material, such as silicon or nitride. Afterwards, a replacement technique is used to remove nitride from an ONON stack and replace it with a conductive material such as tungsten. Afterwards, memory cell films are formed in the memory openings. The conductive material serves as control gates of the memory cells. The control gate will not suffer from corner rounding. ONON shrinkage is avoided, which will prevent control gate shrinkage. Block oxide between the charge storage region and control gate may be deposited after control gate replacement, so the uniformity is good. Block oxide may be deposited after control gate replacement, so TiN adjacent to control gates can be thicker to prevent fluorine attacking the insulator between adjacent control gates. Therefore, control gate to control gate shorting is prevented.