Three-dimensional memory device containing source select gate electrodes with enhanced electrical isolation

Abstract

A method of manufacturing a three-dimensional memory device includes forming, a bottom dielectric layer, a bottom sacrificial material layer, and an alternating stack of insulating layers and spacer material layers over a semiconductor substrate, forming a memory opening, forming an epitaxial channel portion and a memory stack structure in the memory opening, forming a backside contact trench, forming a first backside recess by selectively removing the bottom sacrificial material layer, forming a semiconductor oxide layer underneath the bottom dielectric layer and around a material of the epitaxial channel portion, forming second backside recesses by selectively removing the spacer material layers, and forming electrically conductive layers in the first and second backside recesses.