Sandisk Technologies Inc.

Sandisk Corporation

Sandisk 3d LLC

Henry Chien

George Matamis

James K Kai

Johann Alsmeier

Vinod Robert Purayath

Takashi Whitney Orimoto

Yuan Zhang

Jayavel Pachamuthu

Yao-Sheng Lee

Tuan Duc Pham

Eli Harari

Raghuveer S Makala

Yupin K Fong

George Samachisa

Jack H Yuan

Zhenyu Lu

Masaaki Higashitani

Henry Chin

Jeffrey W Lutze

Donovan Lee

Wenguang Shi

Gheorghe Samachisa

Nima Mokhlesi

Yanli Zhang

Wei Zhao

Xiying Costa

Daxin Mao

Atsushi Suyama

Ming Tian

Hidetaka Horiuchi

Roy E Scheuerlein

Yingda Dong

Christopher John Petti

Dana Lee

Ching-Huang Lu

Tong Zhang

Hiroyuki Kinoshita

Yung-Tin Chen

Chi-Ming Wang

Sateesh Koka

Masanori Terahara

Xiaolong Hu

Hirofumi Watatani

Jian Feng Chen

Er-Xuan Ping

Hiroyuki Ogawa

Peter Rabkin

Gerrit Jan Hemink

Man Lung Mui

Rahul Sharangpani

Hao Fang

Raul Adrian Cernea

Andrew C Lin

Jixin Yu

Thomas Jongwan Kwon

Zhida Lan

Kensuke Yamaguchi

Somesh Peri

Hiro Kinoshita

Matthias Baenninger

Jiyin Xu

Koji Miyata

Akira Takahashi

Andrey Serov

Stephen Shi

Yuichi Ikezono

A stack of alternating layers comprising first epitaxial semiconductor layers and second epitaxial semiconductor layers is formed over a single crystalline substrate. The first and second epitaxial semiconductor layers are in epitaxial alignment with a crystal structure of the single crystalline substrate. The first epitaxial semiconductor layers include a first single crystalline semiconductor material, and the second epitaxial semiconductor layers include a second single crystalline semiconductor material that is different from the first single crystalline semiconductor material. A backside contact opening is formed through the stack, and backside cavities are formed by removing the first epitaxial semiconductor layers selective to the second epitaxial semiconductor layers. A stack of alternating layers including insulating layers and electrically conductive layers is formed. Each insulating layer contains a dielectric material portion deposited within a respective backside cavity. Each electrically conductive layer contains a material from a portion of a respective second epitaxial semiconductor layer.

Crystalline layer stack for forming conductive layers in a three-dimensional memory structure

A method of forming a three-dimensional memory device, includes forming a lower stack structure of insulating and first sacrificial material layers over a substrate, forming first memory openings through the lower stack structure and filling the first memory openings with a sacrificial fill material, replacing the first sacrificial material layers with first electrically conductive layers, forming an upper stack structure of insulating and second sacrificial material layers over the lower stack structure after replacing the first sacrificial material layers, forming second memory openings through the upper stack structure in areas overlying the first memory openings, replacing the second sacrificial material layers with second electrically conductive layers, removing the sacrificial fill material from the first memory openings underneath the second memory openings to form inter-stack memory openings after replacing the second sacrificial material layers, and forming memory stack structures within the inter-stack memory openings.

Method of making a multilevel memory stack structure using a cavity containing a sacrificial fill material

A three dimensional NAND device includes a common vertical channel and electrically isolated control gate electrodes on different lateral sides of the channel in each device level to form different lateral portions of a memory cell in each device level. Dielectric separator structures are located between and electrically isolate the control gate electrodes. The lateral portions of the memory cell in each device level may be electrically isolated by at least one of doping ungated portions of the channel adjacent to the separator structures or storing electrons in the separator structure.

3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same

A memory opening can be formed through a multiple tier structure. Each tier structure includes an alternating stack of sacrificial material layers and insulating layers. After formation of a dielectric oxide layer, the memory opening is filled with a sacrificial memory opening fill structure. The sacrificial material layers are removed selective to the insulating layers and the dielectric oxide layer to form backside recesses. Physically exposed portions of the dielectric oxide layer are removed. A backside blocking dielectric and electrically conductive layers are formed in the backside recesses. Subsequently, the sacrificial memory opening fill structure is replaced with a memory stack structure including a plurality of charge storage regions and a semiconductor channel. Hydrogen or deuterium from a dielectric core may then be outdiffused into the semiconductor channel.

Multi-tier replacement memory stack structure integration scheme

Techniques for forming 3D memory arrays are disclosed. Memory openings are filled with a sacrificial material, such as silicon or nitride. Afterwards, a replacement technique is used to remove nitride from an ONON stack and replace it with a conductive material such as tungsten. Afterwards, memory cell films are formed in the memory openings. The conductive material serves as control gates of the memory cells. The control gate will not suffer from corner rounding. ONON shrinkage is avoided, which will prevent control gate shrinkage. Block oxide between the charge storage region and control gate may be deposited after control gate replacement, so the uniformity is good. Block oxide may be deposited after control gate replacement, so TiN adjacent to control gates can be thicker to prevent fluorine attacking the insulator between adjacent control gates. Therefore, control gate to control gate shorting is prevented.

Forming 3D memory cells after word line replacement

High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.

Non-volatile memory with flat cell structures and air gap isolation

Systems and methods for implementing and using stacked vertical memory array architectures. A first NAND string may be formed or arranged above a second NAND string. The first NAND string may include a first drain-side select gate connected to a first set of memory cell transistors connected to a first source-side select gate. The second NAND string may include a second drain-side select gate connected to a second set of memory cell transistors connected to a second source-side select gate. The first NAND string and the second NAND string may comprise portions of the same or different memory array architectures (e.g., the first NAND string may be part of a memory array that uses U-shaped NAND strings and the second NAND string may be part of a memory array that uses single vertical NAND strings).

Stacked vertical memory array architectures, systems and methods

A method of making a monolithic three dimensional NAND device includes forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming a mask layer over the stack and patterning the mask layer to form at least on opening in the mask layer to expose a top layer of the stack. The method also includes forming a metal block in the at least one opening in the mask layer, etching the stack by metal induced localized etch using the metal block in the at least one opening in the mask layer to form at least one opening in the stack and forming at least one layer of the NAND device in the at least one opening.

High stack 3D memory and method of making

A method of manufacturing a three-dimensional memory device includes forming, a bottom dielectric layer, a bottom sacrificial material layer, and an alternating stack of insulating layers and spacer material layers over a semiconductor substrate, forming a memory opening, forming an epitaxial channel portion and a memory stack structure in the memory opening, forming a backside contact trench, forming a first backside recess by selectively removing the bottom sacrificial material layer, forming a semiconductor oxide layer underneath the bottom dielectric layer and around a material of the epitaxial channel portion, forming second backside recesses by selectively removing the spacer material layers, and forming electrically conductive layers in the first and second backside recesses.

Three-dimensional memory device containing source select gate electrodes with enhanced electrical isolation

A memory device includes a plurality of memory cells arranged in a string substantially perpendicular to the major surface of the substrate in a plurality of device levels, at least one first select gate electrode located between the major surface of the substrate and the plurality of memory cells, at least one second select gate electrode located above the plurality of memory cells, a semiconductor channel having a portion that extends vertically along a direction perpendicular to the major surface, a first memory film contacting a first side of the semiconductor channel, and a second memory film contacting a second side of the semiconductor channel. The second memory film is electrically isolated from the first memory film, and is located at a same level as the first memory film.

A first stack of alternating layers including first electrically conductive layers and first electrically insulating layers is formed with first stepped surfaces and a first dielectric material portion thereupon. Dielectric pillar structures including a dielectric metal oxide can be formed through the first stepped surfaces. Lower memory openings can be formed, and filled with a disposable material or a lower memory opening structure including a lower semiconductor channel and a doped semiconductor region. At least one dielectric material layer and a second stack of alternating layers including second electrically conductive layers and second electrically insulating layers can be sequentially formed. Upper memory openings can be formed through the second stack and the at least one dielectric material layer. A memory film and a semiconductor channel can be formed after removal of the disposable material, or an upper semiconductor channel can be formed on the doped semiconductor region.

Multilevel memory stack structure and methods of manufacturing the same

Peripheral devices for a three-dimensional memory device can be formed over an array of memory stack structures to increase areal efficiency of a semiconductor chip. First contact via structures and first metal lines are formed over an array of memory stack structures and an alternating stack of insulating layers and electrically conductive layers. A semiconductor material layer including a single crystalline semiconductor material or a polycrystalline semiconductor material is formed over first metal lines. After formation of semiconductor devices on or in the semiconductor material layer, metal interconnect structures including second metal lines and additional conductive via structures are formed to electrically connect nodes of the semiconductor devices to respective first metal lines and to memory devices underneath.

Three-dimensional memory device containing CMOS devices over memory stack structures

A memory stack structure for a three-dimensional device includes an alternating stack of insulator layers and spacer material layers. A memory opening is formed through the alternating stack. A memory material layer, a tunneling dielectric layer, and a silicon oxide liner are formed in the memory opening. A sacrificial liner is subsequently formed over the tunneling dielectric layer. The layer stack is anisotropically etched to physically expose a semiconductor surface of the substrate underneath the memory opening. The sacrificial liner may be removed prior to, or after, the anisotropic etch. The silicon oxide liner is removed after the anisotropic etch. A semiconductor channel layer can be deposited directly on the tunneling dielectric layer as a single material layer without any interface therein.

Three-dimensional memory devices having a single layer channel and methods of making thereof

A method of fabricating a semiconductor device, such as a three-dimensional NAND memory string, includes forming a carbon etch stop layer having a first width over a major surface of a substrate, forming a stack of alternating material layers over the etch stop layer, etching the stack to the etch stop layer to form a memory opening having a second width at a bottom of the memory opening that is smaller than the width of the etch stop layer, removing the etch stop layer to provide a void area having a larger width than the second width of the memory opening, forming a memory film over a sidewall of the memory opening and in the void area, and forming a semiconductor channel in the memory opening such that the memory film is located between the semiconductor channel and the sidewall of the memory opening.

Method of integrating select gate source and memory hole for three-dimensional non-volatile memory device

A monolithic three dimensional NAND string including a stack of alternating first material layers and second material layers different from the first material layers over a major surface of a substrate. The first material layers include a plurality of control gate electrodes and the second material layers include an insulating material and the plurality of control gate electrodes extend in a first direction. The NAND string also includes a semiconductor channel, a blocking dielectric, and a plurality of vertically spaced apart floating gates. Each of the plurality of vertically spaced apart floating gates or each of the second material layers includes a first portion having a first thickness in the second direction, and a second portion adjacent to the first portion in the first direction and having a second thickness in the second direction which is different than the first thickness.

Three dimensional vertical NAND device with floating gates

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San Jose, CA, United States of America

Henry Chien