The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2018

Filed:

Mar. 10, 2015
Applicant:

Sandisk Technologies, Inc., Plano, TX (US);

Inventors:

Jayavel Pachamuthu, San Jose, CA (US);

Matthias Baenninger, Menlo Park, CA (US);

Stephen Shi, Milpitas, CA (US);

Johann Alsmeier, San Jose, CA (US);

Henry Chien, San Jose, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 21/336 (2006.01); H01L 21/768 (2006.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 21/76883 (2013.01); H01L 21/28282 (2013.01); H01L 27/11582 (2013.01); H01L 21/7682 (2013.01);
Abstract

A stack of alternating layers comprising first epitaxial semiconductor layers and second epitaxial semiconductor layers is formed over a single crystalline substrate. The first and second epitaxial semiconductor layers are in epitaxial alignment with a crystal structure of the single crystalline substrate. The first epitaxial semiconductor layers include a first single crystalline semiconductor material, and the second epitaxial semiconductor layers include a second single crystalline semiconductor material that is different from the first single crystalline semiconductor material. A backside contact opening is formed through the stack, and backside cavities are formed by removing the first epitaxial semiconductor layers selective to the second epitaxial semiconductor layers. A stack of alternating layers including insulating layers and electrically conductive layers is formed. Each insulating layer contains a dielectric material portion deposited within a respective backside cavity. Each electrically conductive layer contains a material from a portion of a respective second epitaxial semiconductor layer.


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