For the Inventor, By the Inventor

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Milpitas, CA, United States of America

Sandisk 3D LLC

Calculating rank

USPTO Granted Patents = 669

% Expired Patents = 53.1

EPO Patents = 51

Forward Citations = 11,570

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186 inventors (with patents filed for the assignee):

Roy E Scheuerlein (182 out of 270 patents)

Luca Giovanni Fasoli (79 out of 94 patents)

S Brad Herner (68 out of 95 patents)

4. Yun Yu Wang (59 out of 257 patents)

5. Christopher John Petti (52 out of 164 patents)

6. Tanmay Kumar (42 out of 85 patents)

7. Imran Hashim (41 out of 108 patents)

8. Yung-Tin Chen (36 out of 53 patents)

9. Tony P Chiang (35 out of 268 patents)

10. April Dawn Schricker (33 out of 55 patents)

11. Takeshi Yamaguchi (33 out of 137 patents)

12. Tim Minvielle (33 out of 47 patents)

13. Steven J Radigan (33 out of 38 patents)

14. Tyler J Thorp (32 out of 69 patents)

15. Tianhong Yan (31 out of 70 patents)

Core Competencies:

Resistive RAM

Non-Volatile Storage

Atomic Layer Deposition

Memory Architecture

Vertical Bit Lines

Doped Metal Oxides

Memory Cells

Sensing Methods

Multi-Level Arrays

Current Limiting

Transistor Devices

Programming Time

669 patents: Sort by Forward Citations

1. 9786368 - Two stage forming of resistive random access memory cells (2017-10-10),

2. 9543516 - Method for forming a doped metal oxide for use in resistive switching memory elements (2017-01-10),

3. 9425394 - Doped oxide dielectrics for resistive random access memory cells (2016-08-23),

4. 9343673 - Method for forming metal oxides and silicides in a memory device (2016-05-17),

5. 9343507 - Dual channel vertical field effect transistor including an embedded electrode (2016-05-17),

6. 9331088 - Transistor device with gate bottom isolation and method of making thereof (2016-05-03),

7. 9318533 - Methods and systems to reduce location-based variations in switching characteristics of 3D ReRAM arrays (2016-04-19),

8. 9318194 - Apparatus and methods for sensing hard bit and soft bits (2016-04-19),

9. 9299928 - Nonvolatile memory device having a current limiting element (2016-03-29),

10. 9299926 - Nonvolatile memory device using a tunnel oxide layer and oxygen blocking layer as a current limiter element (2016-03-29),

11. 9281029 - Non-volatile memory having 3D array architecture with bit line voltage control and methods thereof (2016-03-08),

12. 9276210 - Conductive barriers for ternary nitride thin-film resistors (2016-03-01),

13. 9276203 - Resistive switching layers including Hf-Al-O (2016-03-01),

14. 9275727 - Multi-level memory array having resistive elements for multi-bit data storage (2016-03-01),

15. 9269902 - Embedded resistors for resistive random access memory cells (2016-02-23),

Company Overview

Sandisk 3D LLC, based in Milpitas, California, specializes in advanced 3D memory technology, focusing on innovative solutions for non-volatile storage. The company is at the forefront of developing resistive RAM and memory architectures that leverage atomic layer deposition techniques. With a commitment to enhancing memory performance, Sandisk 3D LLC explores vertical bit lines and doped metal oxides to create efficient memory cells and sensing methods, positioning itself as a key player in the evolving landscape of memory technology.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 20 2026

669 Patents

#10 in Milpitas, CA

#171 in California

#750 in US

#1,488 in the World

Milpitas, CA, United States of America

Sandisk 3D LLC

Forward Citations = 11,570

186 inventors:

Roy E Scheuerlein (182 out of 270 patents)

Luca Giovanni Fasoli (79 out of 94 patents)

S Brad Herner (68 out of 95 patents)

4. Yun Yu Wang (59 out of 257 patents)

5. Christopher John Petti (52 out of 164 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Sandisk 3D LLC. Retrieved from https://idiyas.com/company/sandisk-3d

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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