The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2016

Filed:

Feb. 20, 2015
Applicants:

Intermolecular Inc., San Jose, CA (US);

Kabushiki Kaisha Toshiba, Tokyo, JP;

Sandisk 3d Llc, Milpitas, CA (US);

Inventors:

Dipankar Pramanik, Saratoga, CA (US);

David E Lazovsky, Los Gatos, CA (US);

Tim Minvielle, San Jose, CA (US);

Takeshi Yamaguchi, Kanagawa, JP;

Assignees:

Intermolecular, Inc., San Jose, CA (US);

Kabushiki Kaisha Toshiba, Tokyo, JP;

SanDisk 3d LLC, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/56 (2006.01); G11C 13/00 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 7/12 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
G11C 11/56 (2013.01); G11C 7/1006 (2013.01); G11C 7/1051 (2013.01); G11C 7/1078 (2013.01); G11C 7/12 (2013.01); G11C 7/22 (2013.01); G11C 11/5685 (2013.01); G11C 13/004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0069 (2013.01); H01L 27/2481 (2013.01); H01L 45/145 (2013.01); H01L 45/1608 (2013.01); G11C 2213/32 (2013.01); G11C 2213/33 (2013.01); G11C 2213/34 (2013.01); G11C 2213/72 (2013.01); H01L 27/2409 (2013.01); H01L 27/2436 (2013.01);
Abstract

A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device. In one configuration, by connecting each memory cell or device with at least one resistor array, a resistive switching layer found in the resistive switching memory element of the connected memory device is capable of being at multiple resistance states for storing multiple bits of digital information. During device programming operations, when a desired series combination of the resistive elements within the resistor array is selected, the resistive switching layer in the connected memory device can be in a desired resistance state.


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