The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2017

Filed:

Dec. 17, 2015
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Jayavel Pachamuthu, San Jose, CA (US);

Johann Alsmeier, San Jose, CA (US);

Henry Chien, San Jose, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 27/115 (2006.01); H01L 29/792 (2006.01); H01L 27/06 (2006.01); H01L 21/822 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); H01L 21/8221 (2013.01); H01L 27/0688 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11551 (2013.01); H01L 27/11575 (2013.01); H01L 27/11578 (2013.01); H01L 27/11582 (2013.01); H01L 27/2481 (2013.01); H01L 29/7926 (2013.01);
Abstract

A first stack of alternating layers including first electrically conductive layers and first electrically insulating layers is formed with first stepped surfaces and a first dielectric material portion thereupon. Dielectric pillar structures including a dielectric metal oxide can be formed through the first stepped surfaces. Lower memory openings can be formed, and filled with a disposable material or a lower memory opening structure including a lower semiconductor channel and a doped semiconductor region. At least one dielectric material layer and a second stack of alternating layers including second electrically conductive layers and second electrically insulating layers can be sequentially formed. Upper memory openings can be formed through the second stack and the at least one dielectric material layer. A memory film and a semiconductor channel can be formed after removal of the disposable material, or an upper semiconductor channel can be formed on the doped semiconductor region.


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