Marko Radosavljevic

Notre Dame, IN, United States of America

Marko Radosavljevic

This inventor holds 397 USPTO granted patents and 123 published patent applications and 26 EPO patents, primarily in Gallium Nitride Technology (CPC class H01L29-2003). Top assignees: Intel Corporation, Tahoe Research, Ltd., Google Inc.. Active years: 2005-2026. Education: Bates College (USA); University of Pennsylvania (USA).

Graduated from:
  • Bates College (USA)
  • University of Pennsylvania (USA)
USPTO Granted Patents = 397 

% Patents Active = 66.2

 

Average Co-Inventor Count = 5.5

ph-index = 20

Forward Citations = 1,659(Granted Patents)

Forward Citations (Not Self Cited) = 1,270(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • Media, PA (US) (2005)
  • Peasantville, NY (US) (2005)
  • Beaverton, OR (US) (2007 - 2024)
  • Portland, OR (US) (2009 - 2024)

Company Filing History:


Years Active: 2005-2026

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Areas of Expertise:
Gallium Nitride
Integrated Circuits
Transistor Structures
Microelectronic Devices
Stacked Transistors
Dielectric Spine
III-N Devices
Capacitance Reduction
Ferroelectric Transistors
Silicide Fabrication
Voltage Regulators
2DEG Layers
397 patents (USPTO):Explore Patents

Stacking the Deck: Marko Radosavljević’s Microscopic High-Rises

When conventional computing hit a planar brick wall, Marko Radosavljević looked at microscopic real estate 

and decided the only sensible solution was to build skyscrapers.

Holding a PhD in physics from the University of Pennsylvania, Radosavljević spent over two decades 

pioneering advanced hardware architectures. As a principal engineer in Intel’s Components Research 

organization, he transformed semiconductor scaling by leading innovations in monolithic 3D integration, 

non-silicon devices, and stacked transistors. Essentially, while the rest of the world struggled to squeeze 

more logic onto crowded silicon wafers, Radosavljević solved the housing crisis by stacking transistors 

on top of each other. 

A prolific inventor, his portfolio boasts numerous patents spanning gallium nitride circuitry, strained contact

architectures, and nanostructures. Now a professor of electrical engineering at the University of Notre Dame 

and an IEEE Senior Member, he continues mentoring the next generation of engineers—ensuring technology 

keeps growing upward. 

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