The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2025

Filed:

Aug. 11, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Seung Hoon Sung, Portland, OR (US);

Willy Rachmady, Beaverton, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Han Wui Then, Portland, OR (US);

Marko Radosavljevic, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/66 (2025.01); H01L 21/28 (2006.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10D 30/43 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01);
U.S. Cl.
CPC ...
H10D 64/671 (2025.01); H01L 21/28114 (2013.01); H10D 30/0273 (2025.01); H10D 30/60 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 64/516 (2025.01); H10D 64/518 (2025.01); H10D 30/43 (2025.01); H10D 30/62 (2025.01); H10D 30/6217 (2025.01); H10D 30/6735 (2025.01);
Abstract

Techniques are disclosed for transistor gate trench engineering to decrease capacitance and resistance. Sidewall spacers, sometimes referred to as gate spacers, or more generally, spacers, may be formed on either side of a transistor gate to help lower the gate-source/drain capacitance. Such spacers can define a gate trench after dummy gate materials are removed from between the spacers to form the gate trench region during a replacement gate process, for example. In some cases, to reduce resistance inside the gate trench region, techniques can be performed to form a multilayer gate or gate electrode, where the multilayer gate includes a first metal and a second metal above the first metal, where the second metal includes lower electrical resistivity properties than the first metal. In some cases, to reduce capacitance inside a transistor gate trench, techniques can be performed to form low-k dielectric material on the gate trench sidewalls.


Find Patent Forward Citations

Loading…