The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 24, 2025
Filed:
Dec. 06, 2021
Intel Corporation, Santa Clara, CA (US);
Cheng-Ying Huang, Hillsboro, OR (US);
Patrick Morrow, Portland, OR (US);
Arunshankar Venkataraman, Mountain View, CA (US);
Sean T. Ma, Portland, OR (US);
Willy Rachmady, Beaverton, OR (US);
Nicole K. Thomas, Portland, OR (US);
Marko Radosavljevic, Portland, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Techniques are provided herein to form semiconductor devices having a stacked transistor configuration. An n-channel device and a p-channel device may both be gate-all-around (GAA) transistors each having any number of nanoribbons extending in the same direction where one device is located vertically above the other device. According to some embodiments, the n-channel device and the p-channel device conductively share the same gate, and a width of the gate structure around one device is greater than the width of the gate structure around the other device. According to some other embodiments, the n-channel device and the p-channel device each have a separate gate structure that is isolated from the other using a dielectric layer between them. A gate contact is adjacent to the upper device and contacts the gate structure of the other lower device.