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For the Inventor, By the Inventor

Portland, OR, United States of America

Nicole K Thomas

This inventor holds 80 USPTO granted patents and 30 published patent applications, primarily in Quantum Dot Devices (CPC class H01L). Top assignees: Intel Corporation, Santa Clara, Other. Active years: 2019-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Nicole K Thomas. Retrieved from https://idiyas.com/inventor/nicole-k-thomas

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 80 

% Patents Active = 85.0

Average Co-Inventor Count = 6.2

ph-index = 6

Forward Citations = 174(Granted Patents)

Forward Citations (Not Self Cited) = 131(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Apopka, FL (US) (2021)
  • Orlando, FL (US) (2020 - 2022)
  • Portland, OR (US) (2019 - 2024)

Company Filing History:

goldMedal76 out of 56,440 
 
Intel Corporation
 patents
silverMedal1 out of 4 
 
Santa Clara
 patents
bronzeMedal2 out of 834,659 
Other
 patents
where one patent can have more than one assignee

Years Active: 2019-2026

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Areas of Expertise:
Quantum Dot Devices
Gallium Nitride
Integrated Circuit
Stacked Transistors
Epitaxial Windows
Optical Communication
Trench-based Devices
Quantum Well Stacks
Selective Dielectric Deposition
Asymmetric Gate Structures
Three-dimensional Technology
Superconducting Qubits
80 patents (USPTO):Explore Patents
1. 12757454 - Stepwise internal spacers for stacked transistor structures (2026-10-06),
2. 12745429 - Diffusion cut stressors for stacked transistors (2026-09-22),
3. 12720819 - Source or drain metallization prior to contact formation in stacked transistors (2026-08-25),
4. 12672355 - Gallium nitride (GaN) epitaxy on patterned substrate for integrated circuit technology (2026-06-30),
5. 12672347 - Lower device access in stacked transistor devices (2026-06-30),
6. 12641850 - Lattice stack for internal spacer fabrication (2026-05-26),
7. 12581717 - Frontside and backside epi contact (2026-03-17),
8. 12550373 - Selective removal of channel bodies in stacked gate-all-around (GAA) device structures (2026-02-10),
9. 12471504 - Trench-based quantum dot devices with conductive liners (2025-11-11),
10. 12471363 - Gate-to-gate isolation for stacked transistor architecture via non-selective dielectric deposition structure (2025-11-11),
11. 12457771 - Plug and recess process for dual metal gate on stacked nanoribbon devices (2025-10-28),
12. 12432964 - Co-integrated gallium nitride (GaN) and complementary metal oxide semiconductor (CMOS) integrated circuit technology (2025-09-30),
13. 12369399 - Gate-to-gate isolation for stacked transistor architecture via selective dielectric deposition structure (2025-07-22),
14. 12342614 - Asymmetric gate structures and contacts for stacked transistors (2025-06-24),
15. 12336268 - Gallium nitride (GaN) integrated circuit technology (2025-06-17),

Title: Inventor Nicole K Thomas: Pioneering Innovations in Portland

Introduction: Nicole K Thomas is a visionary inventor based in Portland, Oregon, known for her groundbreaking contributions to various industries.

Latest Patents: Nicole K Thomas holds several patents in the fields of sustainable energy, biotechnology, and consumer electronics, showcasing her diverse range of expertise.

Career Highlights: With a career spanning over two decades, Nicole has worked with top research institutions and universities to develop cutting-edge technologies that have revolutionized the way we live and work.

Collaborations: Nicole K Thomas has collaborated with leading companies, innovative startups, and renowned inventors to bring her ideas to life and make a lasting impact on society.

Conclusion: Nicole K Thomas continues to inspire the next generation of inventors with her passion for innovation and her dedication to creating a better future for all.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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