The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 2025
Filed:
Aug. 25, 2021
Intel Corporation, Santa Clara, CA (US);
Willy Rachmady, Beaverton, OR (US);
Sudipto Naskar, Portland, OR (US);
Cheng-Ying Huang, Hillsboro, OR (US);
Gilbert Dewey, Beaverton, OR (US);
Marko Radosavljevic, Portland, OR (US);
Nicole K. Thomas, Portland, OR (US);
Patrick Morrow, Portland, OR (US);
Urusa Alaan, Hillsboro, OR (US);
INTEL CORPORATION, Santa Clara, CA (US);
Abstract
An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) and a second semiconductor body (e.g., set of one or more nanoribbons) above the first semiconductor body. The first and second semiconductor bodies are part of the same fin structure. The distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 60 nm or less. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. An isolation structure that includes a dielectric material is between the first and second gate structures, and is on and conformal to a top surface of the first gate structure. In addition, a bottom surface of the second gate structure is on a top surface of the isolation structure, which is relatively flat.