Gilbert W Dewey

Beaverton, OR, United States of America

Gilbert W Dewey

This inventor holds 418 USPTO granted patents and 83 published patent applications and 31 EPO patents, primarily in Transistor Technology (CPC class H01L29-785). Top assignees: Intel Corporation, Google Inc., Tahoe Research, Ltd.. Active years: 2006-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Gilbert W Dewey. Retrieved from https://idiyas.com/inventor/gilbert-w-dewey

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 418 

% Patents Active = 74.6

 

Average Co-Inventor Count = 7.0

ph-index = 16

Forward Citations = 1,315(Granted Patents)

Forward Citations (Not Self Cited) = 1,080(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • Beaveton, OR (US) (2022)
  • Hillsoboro, OR (US) (2023)
  • Hillsboro, OR (US) (2006 - 2024)
  • Beaverton, OR (US) (2017 - 2024)

Company Filing History:


Years Active: 2006-2026

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Areas of Expertise:
Transistor Structures
Contact Resistance
Silicon Germanium
Thin Film Transistors
CMOS Architecture
Epitaxial Contacts
Stacked Transistors
Ferroelectric Gates
Memory Cells
Nanoribbons
Gate Isolation
Metal Oxide Contacts
418 patents (USPTO):Explore Patents

Title: The Innovations of Gilbert W. Dewey

Introduction

Gilbert W. Dewey is a prominent inventor based in Beaverton, OR (US), known for his significant contributions to the field of integrated circuit technology. With an impressive portfolio of 418 patents, Dewey has made substantial advancements that have influenced modern electronics.

Latest Patents

Among his latest patents is a groundbreaking invention titled "Lower device access in stacked transistor devices." This patent describes an integrated circuit structure that includes a device layer with an upper device positioned above a lower device. The upper device features an upper source or drain region, along with a corresponding contact. The lower device contains a lower source or drain region, with a first conductive feature located below the device layer, facilitating connections between the interconnect structure and the lower source or drain region. Another notable patent focuses on "Low-resistance and thermally stable contacts with phosphide or arsenide metal compound layers." This invention addresses the formation of contacts to n-type source/drain regions, utilizing phosphide or arsenide metal compound layers to create thermally stable, low-resistance contacts. These layers prevent the diffusion of dopants and enhance the reliability of the integrated circuits.

Career Highlights

Dewey has had a distinguished career, working with leading technology companies such as Intel Corporation and Google Inc. His work has been instrumental in advancing semiconductor technology and improving the performance of electronic devices.

Collaborations

Throughout his career, Dewey has collaborated with notable professionals in the field, including Jack T. Kavalieros and Willy Rachmady. These collaborations have further enriched his contributions to innovation in integrated circuits.

Conclusion

Gilbert W. Dewey's extensive patent portfolio and innovative work in integrated circuit technology have made a lasting impact on the electronics industry. His inventions continue to shape the future of technology and enhance the performance of electronic devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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