The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

Dec. 20, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Gilbert Dewey, Beaverton, OR (US);

Cheng-Ying Huang, Hillsboro, OR (US);

Nicole K. Thomas, Portland, OR (US);

Marko Radosavljevic, Portland, OR (US);

Patrick Morrow, Portland, OR (US);

Ashish Agrawal, Hillsboro, OR (US);

Willy Rachmady, Beaverton, OR (US);

Seung Hoon Sung, Portland, OR (US);

Christopher M. Neumann, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/01 (2025.01); H01L 23/48 (2006.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 84/0149 (2025.01); H01L 23/481 (2013.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01);
Abstract

Techniques are provided herein to form semiconductor devices having a frontside and backside contact in an epi region of a stacked transistor configuration. In one example, an n-channel device and a p-channel device may both be GAA transistors where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device. Deep and narrow contacts may be formed from both the frontside and the backside of the integrated circuit through the stacked source or drain regions. The contacts may physically contact each other to form a combined contact that extends through an entirety of the stacked source or drain regions. The higher contact area provided to both source or drain regions provides a more robust ohmic contact with a lower contact resistance compared to previous contact architectures.


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