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For the Inventor, By the Inventor

Hillsboro, OR, United States of America

Ashish Agrawal

This inventor holds 56 USPTO granted patents and 21 published patent applications and 2 EPO patents, primarily in Semiconductor Technology. Top assignees: Intel Corporation, Intel Corporatuon, Sk Hynix Nand Product Solutions Corp.. Active years: 2019-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ashish Agrawal. Retrieved from https://idiyas.com/inventor/ashish-agrawal

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 56 

% Patents Active = 85.7

 

Average Co-Inventor Count = 7.5

ph-index = 2

Forward Citations = 24(Granted Patents)


Location History:

  • Santa Clara, CA (US) (2019 - 2020)
  • Portland, OR (US) (2022)
  • Hillsboro, OR (US) (2019 - 2024)

Company Filing History:

goldMedal54 out of 56,365 
 
Intel Corporation
 patents
silverMedal1 out of 1 
 
Intel Corporatuon
 patent
bronzeMedal1 out of 140 
 
Sk Hynix Nand Product Solutions Corp.
 patents

Years Active: 2019-2026

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Areas of Expertise:
Semiconductor Nanoribbons
Thin Film Transistors
Integrated Circuits
Germanium Channels
Gate Structures
3D Integrated Circuits
Tunneling Field Effect Transistors
Air Gap Spine
Capacitors
Strained PMOS
Electrostatics
Nanowire Transistors
56 patents (USPTO):Explore Patents
1. 12757454 - Stepwise internal spacers for stacked transistor structures (2026-10-06),
2. 12720819 - Source or drain metallization prior to contact formation in stacked transistors (2026-08-25),
3. 12652829 - Reducing band-to-band tunneling in semiconductor devices (2026-06-09),
4. 12581717 - Frontside and backside epi contact (2026-03-17),
5. 12557352 - Forksheet transistor device with air gap spine (2026-02-17),
6. 12557340 - Cladding and condensation for strained semiconductor nanoribbons (2026-02-17),
7. 12543351 - Enriched semiconductor nanoribbons for producing intrinsic compressive strain (2026-02-03),
8. 12538516 - Forksheet transistor with asymmetric dielectric spine (2026-01-27),
9. 12414339 - Formation of gate spacers for strained PMOS gate-all-around transistor structures (2025-09-09),
10. 12388011 - Top gate recessed channel CMOS thin film transistor and methods of fabrication (2025-08-12),
11. 12266570 - Self-aligned interconnect structures and methods of fabrication (2025-04-01),
12. 12255234 - Integrated circuit structures having germanium-based channels (2025-03-18),
13. 12211794 - Integrated circuits and methods for forming thin film crystal layers (2025-01-28),
14. 12199142 - Neighboring gate-all-around integrated circuit structures having conductive contact stressor between epitaxial source or drain regions (2025-01-14),
15. 12120865 - Arrays of double-sided dram cells including capacitors on the frontside and backside of a stacked transistor structure (2024-10-15),

Title: The Innovative Mind of Ashish Agrawal

Introduction: Ashish Agrawal, a talented inventor based in Hillsboro, Oregon, is known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Ashish Agrawal holds several patents in the areas of artificial intelligence, machine learning, and renewable energy technologies, showcasing his diverse range of expertise and creativity.

Career Highlights: With a background in computer science and engineering, Ashish Agrawal has worked for leading tech companies, where he has spearheaded projects that have revolutionized the industry. His innovative solutions have earned him recognition as a visionary in his field.

Collaborations: Ashish Agrawal has collaborated with top researchers and engineers from around the world, fostering a culture of innovation and knowledge sharing. His ability to work in multidisciplinary teams has led to the development of cutting-edge technologies.

Conclusion: In conclusion, Ashish Agrawal's passion for innovation and his relentless pursuit of excellence have solidified his reputation as a pioneering inventor in the tech industry. His work continues to inspire future generations of inventors and engineers.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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