The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2025
Filed:
Dec. 23, 2020
Intel Corporation, Santa Clara, CA (US);
Kimin Jun, Portland, OR (US);
Souvik Ghosh, Beaverton, OR (US);
Willy Rachmady, Beaverton, OR (US);
Ashish Agrawal, Hillsboro, OR (US);
Siddharth Chouksey, Portland, OR (US);
Jessica Torres, Portland, OR (US);
Jack Kavalieros, Portland, OR (US);
Matthew Metz, Portland, OR (US);
Ryan Keech, Portland, OR (US);
Koustav Ganguly, Beaverton, OR (US);
Anand Murthy, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.