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For the Inventor, By the Inventor

Portland, OR, United States of America

Ryan Keech

This inventor holds 18 USPTO granted patents and 8 published patent applications, primarily in CMOS Transistor Technology. Top assignee: Intel Corporation. Active years: 2021-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ryan Keech. Retrieved from https://idiyas.com/inventor/ryan-keech

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 18 

% Patents Active = 100.0

Average Co-Inventor Count = 6.7

ph-index = 2

Forward Citations = 9(Granted Patents)


Company Filing History:

goldMedal18 out of 56,394 
 
Intel Corporation
 patents

Years Active: 2021-2025

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Areas of Expertise:
CMOS Transistors
Thin Film Transistor
3D Integrated Circuits
Contact Resistance
Source Drain Structures
Metallization
Epitaxial Regions
Dopant Profiles
Vertical Trenches
Monocrystalline Channels
High Aspect Ratio
18 patents (USPTO):Explore Patents
1. 12388011 - Top gate recessed channel CMOS thin film transistor and methods of fabrication (2025-08-12),
2. 12342611 - Source or drain structures with vertical trenches (2025-06-24),
3. 12342574 - Contact resistance reduction in transistor devices with metallization on both sides (2025-06-24),
4. 12288808 - High aspect ratio source or drain structures with abrupt dopant profile (2025-04-29),
5. 12266570 - Self-aligned interconnect structures and methods of fabrication (2025-04-01),
6. 12119387 - Low resistance approaches for fabricating contacts and the resulting structures (2024-10-15),
7. 12094881 - Arsenic-doped epitaxial source/drain regions for NMOS (2024-09-17),
8. 11996404 - Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material (2024-05-28),
9. 11973143 - Source or drain structures for germanium N-channel devices (2024-04-30),
10. 11935887 - Source or drain structures with vertical trenches (2024-03-19),
11. 11929320 - Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication (2024-03-12),
12. 11804523 - High aspect ratio source or drain structures with abrupt dopant profile (2023-10-31),
13. 11610889 - Arsenic-doped epitaxial, source/drain regions for NMOS (2023-03-21),
14. 11552169 - Source or drain structures with phosphorous and arsenic co-dopants (2023-01-10),
15. 11482621 - Vertically stacked CMOS with upfront M0 interconnect (2022-10-25),

Title: The Innovative Journey of Ryan Keech

Introduction: Ryan Keech, a talented inventor based in Portland, Oregon, has been making waves in the world of technology with his groundbreaking creations.

Latest Patents: Ryan Keech holds several patents in the field of renewable energy technologies, including a solar panel design that increases efficiency by 30%.

Career Highlights: With over a decade of experience in the industry, Ryan has worked for top tech companies, leading research institutions, and universities, contributing significantly to advancements in clean energy solutions.

Collaborations: Throughout his career, Ryan Keech has collaborated with renowned engineers, scientists, and environmentalists, fostering a culture of innovation and sustainability in all his projects.

Conclusion: Ryan Keech's passion for innovation and dedication to creating a greener future make him a true pioneer in the field of renewable energy technologies.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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