The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 28, 2024
Filed:
Dec. 01, 2021
Intel Corporation, Santa Clara, CA (US);
Cheng-Ying Huang, Hillsboro, OR (US);
Gilbert Dewey, Hillsboro, OR (US);
Ashish Agrawal, Hillsboro, OR (US);
Kimin Jun, Portland, OR (US);
Willy Rachmady, Beaverton, OR (US);
Zachary Geiger, Hillsboro, OR (US);
Cory Bomberger, Portland, OR (US);
Ryan Keech, Portland, OR (US);
Koustav Ganguly, Hillsboro, OR (US);
Anand Murthy, Portland, OR (US);
Jack Kavalieros, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.