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For the Inventor, By the Inventor

Hillsboro, OR, United States of America

Cheng-Ying Huang

This inventor holds 99 USPTO granted patents and 34 published patent applications and 1 EPO patent, primarily in Stacked Transistor Technology (CPC class H01L29-785). Top assignee: Intel Corporation. Active years: 2020-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Cheng-Ying Huang. Retrieved from https://idiyas.com/inventor/cheng-ying-huang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 99 

% Patents Active = 91.9

 

Average Co-Inventor Count = 7.9

ph-index = 3

Forward Citations = 58(Granted Patents)

Forward Citations (Not Self Cited) = 27(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • Hillsboro, OR (US) (2020 - 2024)
  • Portland, OR (US) (2020 - 2024)
  • kPortland, OR (US) (2024)

Company Filing History:

goldMedal98 out of 56,290 
 
Intel Corporation
 patents
where one patent can have more than one assignee

Years Active: 2020-2026

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Areas of Expertise:
Stacked Transistors
CMOS Architecture
Gate-All-Around Structures
Interconnect Techniques
Thin Film Transistors
Ferroelectric Gate Stack
Vertical Tunneling FETs
Epitaxial Layers
3D Integrated Circuits
Non-Silicon Transistors
Source-Drain Connections
Dielectric Isolation
99 patents (USPTO):Explore Patents
1. 12757454 - Stepwise internal spacers for stacked transistor structures (2026-10-06),
2. 12745429 - Diffusion cut stressors for stacked transistors (2026-09-22),
3. 12745428 - 3D source and drain contacts tuned for vertically stacked PMOS and NMOS (2026-09-22),
4. 12733229 - Nanoribbon stacks without dielectric protection caps for top nanoribbons (2026-09-08),
5. 12727205 - 3D source and drain contacts tuned for PMOS and NMOS (2026-09-01),
6. 12720819 - Source or drain metallization prior to contact formation in stacked transistors (2026-08-25),
7. 12672347 - Lower device access in stacked transistor devices (2026-06-30),
8. 12666692 - Vertical diodes in stacked transistor technologies (2026-06-23),
9. 12641850 - Lattice stack for internal spacer fabrication (2026-05-26),
10. 12598814 - Lateral diodes in stacked transistor technologies (2026-04-07),
11. 12581717 - Frontside and backside epi contact (2026-03-17),
12. 12575184 - CMOS architecture with thermally stable silicide gate workfunction metal (2026-03-10),
13. 12550373 - Selective removal of channel bodies in stacked gate-all-around (GAA) device structures (2026-02-10),
14. 12414339 - Formation of gate spacers for strained PMOS gate-all-around transistor structures (2025-09-09),
15. 12388011 - Top gate recessed channel CMOS thin film transistor and methods of fabrication (2025-08-12),

Title: The Innovative Journey of Cheng-Ying Huang

Introduction: Cheng-Ying Huang, a talented inventor based in Hillsboro, Oregon, has made significant contributions to the field of technology through his groundbreaking innovations and patents.

Latest Patents: Huang's latest patents focus on advancements in semiconductor technology, particularly in the development of cutting-edge microprocessors and memory storage devices.

Career Highlights: With a career spanning over two decades, Cheng-Ying Huang has worked for leading tech companies, where he played a key role in the research and development of next-generation electronic devices. His expertise in semiconductor engineering has led to the successful commercialization of several groundbreaking products.

Collaborations: Throughout his career, Huang has collaborated with top researchers, engineers, and scientists in the industry. His ability to work effectively in multidisciplinary teams has resulted in the successful implementation of innovative solutions to complex technological challenges.

Conclusion: Cheng-Ying Huang's passion for innovation and his relentless pursuit of excellence have established him as a prominent figure in the world of technology. His contributions continue to shape the future of semiconductor engineering, inspiring the next generation of inventors and engineers.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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