The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2024
Filed:
Mar. 28, 2019
Intel Corporation, Santa Clara, CA (US);
Ryan Keech, Portland, OR (US);
Benjamin Chu-Kung, Portland, OR (US);
Subrina Rafique, Hillsboro, OR (US);
Devin Merrill, McMinnville, OR (US);
Ashish Agrawal, Hillsboro, OR (US);
Harold Kennel, Portland, OR (US);
Yang Cao, Beaverton, OR (US);
Dipanjan Basu, Hillsboro, OR (US);
Jessica Torres, Portland, OR (US);
Anand Murthy, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.