The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2026

Filed:

Nov. 22, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ashish Agrawal, Hillsboro, OR (US);

Christopher M. Neumann, Portland, OR (US);

Seung Hoon Sung, Portland, OR (US);

Marko Radosavljevic, Portland, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01);
U.S. Cl.
CPC ...
H10D 62/116 (2025.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01);
Abstract

Techniques are provided herein to form a forksheet device with an air gap spine. The air gap may be devoid of gas, or not. In an example, the device includes a first semiconductor body laterally extending from a first side of a void (air gap) and having an end surface that defines part of the first side of the void, and a second semiconductor body laterally extending from a second side of the void and having an end surface that defines part of the second side of the void. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. In some cases, a spacer structure is between a source or drain region and the corresponding gate structure, the spacer structure including one or more portions of the void. The void may be created with a backside process, post-device formation.


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