Intel Corporation

Google Inc.

Tahoe Research, Ltd.

Intel Corproation

Gilbert W Dewey

Jack T Kavalieros

Willy Rachmady

Matthew V Metz

Ravi Pillarisetty

Marko Radosavljevic

Van H Le

Benjamin Chu-Kung

Tahir Ghani

Niloy Mukherjee

Robert S Chau

Abhishek A Sharma

Cheng-Ying Huang

Anand S Murthy

Aaron D Lilak

Sean T Ma

Patrick R Morrow

Anh Phan

Chandra S Mohapatra

Harold W Kennel

Han Wui Then

Shriram Shivaraman

Seung Hoon Sung

Ehren Mannebach

Rishabh Mehandru

Rafael Rios

Niti Goel

Hui Jae Yoo

Glenn A Glass

Mantu K Hudait

Suman Datta

Justin K Brask

Nazila Haratipour

Ashish Agrawal

Sansaptak W Dasgupta

Mark L Doczy

Sanaz Kabehie Gardner

Titash Rakshit

Roza Kotlyar

Nicholas G Minutillo

Prashant Majhi

Kimin Jun

Justin R Weber

Uday Shah

Nancy M Zelick

Brian S Doyle

Christopher J Jezewski

Yih Wang

Ryan Keech

Stephen M Cea

Cory C Bomberger

Nadia M Rahhal-Orabi

Tristan A Tronic

Arnab Sen Gupta

Jessica S Kachian

Stephanie A Bojarski

Ian A Young

Telesphor Kamgaing

Uygar E Avci

Been-Yih Jin

Richard E Schenker

Scott Bruce Clendenning

Miriam Ruth Reshotko

Hyung-Jin Lee

Aleksandar Aleksov

Georgios C Dogiamis

Charles C Kuo

Kelin J Kuhn

Markus Kuhn

Siddharth Chouksey

Anurag Chaudhry

Kevin Lai Lin

Nicole K Thomas

Karthik Jambunathan

James M Powers

Valluri Ramana Rao

Dinesh Somasekhar

Mauro J Kobrinsky

Seiyon Kim

Wilman Tsai

Cory E Weber

Satyarth Suri

Nafees Kabir

Urusa Alaan

Jeffery D Bielefeld

Brennen Karl Mueller

Jessica M Torres

Chi-Hwa Tsang

Johanna M Swan

Adel A Elsherbini

Henning Braunisch

Elijah V Karpov

Leonard P Guler

Rami Hourani

Wilfred Gomes

Nick Lindert

Daniel Bourne Aubertine

Lawrence D Wong

Patricio E Romero

Jose A Maiz

Techniques are provided herein to form semiconductor devices having epitaxial diffusion regions (e.g., source and/or drain regions) wrapped by a conductive contact. In an example, a semiconductor device includes a source or drain region and a conductive layer that extends around the source or drain region such that the conductive layer at least contacts the sidewalls of the source or drain region or wraps completely around the source or drain region. In some examples, a conducive contact extends upward through a thickness of an adjacent dielectric layer and contacts the conductive layer from below, thus forming a backside contact. By forming a conductive layer around multiple sides of the source or drain region (rather than just contacting a top or bottom surface) more surface area of the source or drain region is contacted thus providing an improved ohmic contact and a lower overall contact resistance.

Conductive contacts wrapped around epitaxial source or drain regions

Source and drain contacts that provide improved contact resistance and contact interface stability for transistors employing silicon and germanium source and drain materials, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such source and drain contacts include a contact layer of co-deposited titanium and silicon on the silicon and germanium source and drain. The disclosed source and drain contacts improve transistor performance including switching speed and reliability.

Co-deposition of titanium and silicon for improved silicon germanium source and drain contacts

Embodiments disclosed herein include semiconductor devices with improved contact resistances. In an embodiment, a semiconductor device comprises a semiconductor channel, a gate stack over the semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, and contacts over the source region and the drain region. In an embodiment, the contacts comprise a silicon germanium layer, an interface layer over the silicon germanium layer, and a titanium layer over the interface layer.

Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability

A gate-all-around transistor device includes a body including a semiconductor material, and a gate structure at least in part wrapped around the body. The gate structure includes a gate electrode and a gate dielectric between the body and the gate electrode. The body is between a source region and a drain region. A first spacer is between the source region and the gate electrode, and a second spacer is between the drain region and the gate electrode. In an example, the first and second spacers include germanium and oxygen. The body can be, for instance, a nanoribbon, nanosheet, or nanowire.

Formation of gate spacers for strained PMOS gate-all-around transistor structures

A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

Top gate recessed channel CMOS thin film transistor and methods of fabrication

FETs including a gated oxide semiconductor spacer interfacing with a channel semiconductor. Transistors may incorporate a non-oxide channel semiconductor, and one or more oxide semiconductors disposed proximal to the transistor gate electrode and the source/drain semiconductor, or source/drain contact metal. In advantageous embodiments, the oxide semiconductor is to be gated by a voltage applied to the gate electrode (i.e., gate voltage) so as to switch the oxide semiconductor between insulating and semiconducting states in conjunction with gating the transistor's non-oxide channel semiconductor between on and off states.

Field effect transistors with a gated oxide semiconductor source/drain spacer

An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) and a second semiconductor body (e.g., set of one or more nanoribbons) above the first semiconductor body. The first and second semiconductor bodies are part of the same fin structure. The distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 60 nm or less. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. An isolation structure that includes a dielectric material is between the first and second gate structures, and is on and conformal to a top surface of the first gate structure. In addition, a bottom surface of the second gate structure is on a top surface of the isolation structure, which is relatively flat.

Gate-to-gate isolation for stacked transistor architecture via selective dielectric deposition structure

Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

Transistor structures with a metal oxide contact buffer and a method of fabricating the transistor structures

Embodiments disclosed herein include transistor devices and methods of making such devices. In an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. In an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. In an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. In an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer.

Contact resistance reduction in transistor devices with metallization on both sides

Low resistance and reduced reactivity approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is on the first or second semiconductor source or drain structure, the source or drain contact including an alloyed metal barrier layer and an inner conductive structure.

Low resistance and reduced reactivity approaches for fabricating contacts and the resulting structures

A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

Transistor with isolation below source and drain

Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.

Sideways vias in isolation areas to contact interior layers in stacked devices

Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.

Forming an oxide volume within a fin

Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.

Dual gate control for trench shaped thin film transistors

Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (V). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vwithin the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.

Ribbon or wire transistor stack with selective dipole threshold voltage shifter

Growing community of inventors

Beaverton, OR, United States of America

Gilbert W Dewey