Gate-to-gate isolation for stacked transistor architecture via non-selective dielectric deposition structure

Abstract

An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) and a second semiconductor body (e.g., set of one or more nanoribbons) above the first semiconductor body. The first and second semiconductor bodies are part of the same fin structure. The distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 60 nm or less. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. An isolation structure that includes a dielectric material is between the first and second gate structures, and on the first gate structure. In addition, at least a portion of the second gate structure is on a central portion of the isolation structure and between first and second end portions of the isolation structure.