The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2025

Filed:

Sep. 15, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Han Wui Then, Portland, OR (US);

Marko Radosavljevic, Portland, OR (US);

Nicole K. Thomas, Portland, OR (US);

Pratik Koirala, Portland, OR (US);

Nityan Nair, Portland, OR (US);

Paul B. Fischer, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/42 (2005.12); G06F 1/16 (2005.12);
U.S. Cl.
CPC ...
G02B 6/4274 (2012.12); G06F 1/1686 (2012.12); G06F 1/1698 (2012.12);
Abstract

Gallium nitride (GaN) integrated circuit technology with optical communication is described. In an example, an integrated circuit structure includes a layer or substrate having a first region and a second region, the layer or substrate including gallium and nitrogen. A GaN-based device is in or on the first region of the layer or substrate. A CMOS-based device is over the second region of the layer or substrate. An interconnect structure is over the GaN-based device and over the CMOS-based device, the interconnect structure including conductive interconnects and vias in a dielectric layer. A photonics waveguide is over the interconnect structure, the photonics waveguide including silicon, and the photonics waveguide bonded to the dielectric layer of the interconnect structure.


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