The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2025
Filed:
Aug. 23, 2021
Intel Corporation, Santa Clara, CA (US);
Punyashloka Debashis, Hillsboro, OR (US);
Dmitri Evgenievich Nikonov, Beaverton, OR (US);
Hai Li, Portland, OR (US);
Chia-Ching Lin, Portland, OR (US);
Raseong Kim, Portland, OR (US);
Tanay A. Gosavi, Portland, OR (US);
Ashish Verma Penumatcha, Beaverton, OR (US);
Uygar E. Avci, Portland, OR (US);
Marko Radosavljevic, Portland, OR (US);
Ian Alexander Young, Olympia, WA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A pbit device, in one embodiment, includes a first field-effect transistor (FET) that includes a source region, a drain region, a source electrode on the source region, a drain electrode on the drain region, a channel region between the source and drain regions, a dielectric layer on a surface over the channel region, an electrode layer above the dielectric layer, and a ferroelectric (FE) material layer between the dielectric layer and the electrode layer. The pbit device also includes a second FET comprising a source electrode, a drain electrode, and a gate electrode. The drain electrode of the second FET is connected to the drain electrode of the first FET.