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DaeSik Choi

This inventor holds 78 USPTO granted patents and 10 published patent applications, primarily in Integrated Circuit Packaging (CPC class H01L). Top assignees: Stats Chippac Pte. Ltd., Jcet Semiconductor (Shaoxing) Co., Ltd., Sts Semiconductor & Telecommunications Co., Ltd.. Active years: 2011-2020.

USPTO Granted Patents = 78 (Patent Applications = 10)

% Patents Active = 98.7

Average Co-Inventor Count = 3.1

ph-index = 11

Forward Citations = 767(Granted Patents)

Forward Citations (Not Self Cited) = 740(Dec 10, 2025)

Inventors with similar research interests:

Company Filing History:

76 out of 1,842

Stats Chippac Pte. Ltd.

patents

1 out of 15

Jcet Semiconductor (Shaoxing) Co., Ltd.

patents

1 out of 16

Sts Semiconductor & Telecommunications Co., Ltd.

patents

Years Active: 2011-2020

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Areas of Expertise:

Semiconductor Device

Integrated Circuit

Wafer Singulation

Thermal Management

Chip Stacking

Interconnect Structure

WLCSP

Conductive Pads

Vertical Interconnection

Underfill Material

Warpage Prevention

Heat Dissipation

78 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 10665534 - Semiconductor device and method of using partial wafer singulation for improved wafer level embedded system in package (2020-05-26),

2. 10163744 - Semiconductor device and method of forming a low profile dual-purpose shield and heat-dissipation structure (2018-12-25),

3. 10068877 - Semiconductor device and method of forming WLCSP with semiconductor die embedded within interconnect structure (2018-09-04),

4. 9799590 - Semiconductor device and method of using partial wafer singulation for improved wafer level embedded system in package (2017-10-24),

5. 9530753 - Integrated circuit packaging system with chip stacking and method of manufacture thereof (2016-12-27),

6. 9406579 - Semiconductor device and method of controlling warpage in semiconductor package (2016-08-02),

7. 9401289 - Semiconductor device and method of backgrinding and singulation of semiconductor wafer while reducing kerf shifting and protecting wafer surfaces (2016-07-26),

8. 9390945 - Semiconductor device and method of depositing underfill material with uniform flow rate (2016-07-12),

9. 9378983 - Semiconductor device and method of mounting cover to semiconductor die and interposer with adhesive material (2016-06-28),

10. 9373578 - Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties (2016-06-21),

11. 9349666 - Integrated circuit packaging system with package stacking (2016-05-24),

12. 9349616 - Semiconductor device and method of forming WLCSP with semiconductor die embedded within interconnect structure (2016-05-24),

13. 9324659 - Semiconductor device and method of forming POP with stacked semiconductor die and bumps formed directly on the lower die (2016-04-26),

14. 9312218 - Semiconductor device and method of forming leadframe with conductive bodies for vertical electrical interconnect of semiconductor die (2016-04-12),

15. 9305897 - Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate (2016-04-05),

Title: Innovations by DaeSik Choi: A Leader in Semiconductor Technology

Introduction

DaeSik Choi, an accomplished inventor based in Seoul, South Korea, has made significant contributions to the field of semiconductor technology. With an impressive portfolio of 78 patents, his work focuses on innovative devices and methodologies that enhance the functionality and efficiency of semiconductor systems.

Latest Patents

Among his most recent patents is a noteworthy invention titled "Semiconductor device and method of using partial wafer singulation for improved wafer level embedded system in package." This invention introduces a semiconductor device comprising a semiconductor wafer with multiple first semiconductor die, designed with a partial opening. The patent outlines a process in which second semiconductor die are disposed over the first surface of the wafer, allowing for advanced encapsulation techniques that improve thermal management and interconnectivity.

Another significant patent authored by Choi is titled "Semiconductor device and method of forming a low profile dual-purpose shield and heat-dissipation structure." This innovative design features a substrate with a recess and incorporates a planar heat spreader strategically mounted for optimal heat dissipation. The arrangement of semiconductor die and bond wires facilitates enhanced electrical connectivity and performance, owing to the meticulous engineering of the conductive vias.

Career Highlights

DaeSik Choi's journey is marked by impactful roles at prominent companies in the semiconductor industry. He has contributed his expertise during his tenure at Stats Chippac Pte. Ltd. and Sts Semiconductor & Telecommunications Co., Ltd. His engineering skills and inventive mindset have been pivotal in driving technological advancements within these organizations.

Collaborations

Throughout his career, DaeSik Choi has collaborated with industry professionals, including noteworthy coworkers such as SungWon Cho and KyungHoon Lee. Such collaborations have fostered a creative environment that encourages innovation and the development of cutting-edge semiconductor solutions.

Conclusion

DaeSik Choi stands out as a leading inventor in the semiconductor field, with a rich background characterized by numerous patents and collaborative efforts. His latest inventions not only demonstrate his technical capabilities but also contribute to advancing the semiconductor industry, paving the way for future innovations.

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