The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

Dec. 23, 2013
Applicant:

Stats Chippac, Ltd., Singapore, SG;

Inventors:

DaeSik Choi, Seoul, KR;

JongHo Kim, Gyeonggi, KR;

HyungMin Lee, Gyeonggi-do, KR;

Assignee:

STATS ChipPAC, Ltd., Singapore, SG;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 23/00 (2006.01); H01L 21/683 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 23/552 (2006.01); H01L 25/065 (2006.01); H01L 25/10 (2006.01); H01L 25/00 (2006.01); H01L 23/522 (2006.01); H01L 23/48 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H05K 3/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/82 (2013.01); H01L 21/6835 (2013.01); H01L 23/3121 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 23/5226 (2013.01); H01L 23/5389 (2013.01); H01L 23/552 (2013.01); H01L 24/29 (2013.01); H01L 24/95 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 23/3107 (2013.01); H01L 23/3672 (2013.01); H01L 23/481 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 2221/68331 (2013.01); H01L 2221/68363 (2013.01); H01L 2221/68381 (2013.01); H01L 2221/68386 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05611 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05639 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/29 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/29101 (2013.01); H01L 2224/29144 (2013.01); H01L 2224/29187 (2013.01); H01L 2224/29298 (2013.01); H01L 2224/48105 (2013.01); H01L 2224/48175 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48228 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81192 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/95001 (2013.01); H01L 2224/96 (2013.01); H01L 2224/97 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06572 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/00013 (2013.01); H01L 2924/0103 (2013.01); H01L 2924/01004 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/0105 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01032 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/01049 (2013.01); H01L 2924/01073 (2013.01); H01L 2924/01074 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/0665 (2013.01); H01L 2924/09701 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/12041 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15321 (2013.01); H01L 2924/15331 (2013.01); H01L 2924/181 (2013.01); H01L 2924/3025 (2013.01); H05K 3/007 (2013.01); H05K 3/0052 (2013.01); H05K 3/0097 (2013.01);
Abstract

A semiconductor device includes a wafer level substrate having a plurality of first conductive vias formed through the wafer level substrate. A first semiconductor die is mounted to the wafer level substrate. A first surface of the first semiconductor die includes contact pads oriented toward a first surface of the wafer level substrate. A first encapsulant is deposited over the first semiconductor die. A second semiconductor die is mounted to the wafer level substrate. A first surface of the second semiconductor die includes contact pads oriented toward a second surface of the wafer level substrate opposite the first surface of the wafer level substrate. A second encapsulant is deposited over the second semiconductor die. A plurality of bumps is formed over the plurality of first conductive vias. A second conductive via can be formed through the first encapsulant and connected to the first conductive via. The semiconductor packages are stackable.


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