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Shaoxing, China

Jcet Semiconductor (Shaoxing) Co., Ltd.

USPTO Granted Patents = 15

Forward Citations = 5

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38 inventors (with patents filed for the assignee):

Yaojian Lin (4 out of 290 patents)

Reza A Pagaila (4 out of 192 patents)

Yung Kuan Hsiao (3 out of 11 patents)

4. Yoke Hor Phua (3 out of 6 patents)

5. Seung Uk Yoon (3 out of 17 patents)

6. Kang Chen (2 out of 118 patents)

7. Seung Wook Yoon (2 out of 22 patents)

8. See Chian Lim (2 out of 6 patents)

9. Teck Tiong Tan (2 out of 4 patents)

10. Ching Meng Fang (2 out of 8 patents)

11. Bartholomew Liao (2 out of 5 patents)

12. Jianmin Fang (2 out of 59 patents)

13. Seng Guan Chow (2 out of 207 patents)

14. Byung Tai Do (2 out of 227 patents)

15. Linda Pei Ee Chua (2 out of 127 patents)

15 patents: Sort by Forward Citations

1. 12148677 - Semiconductor device and method of forming ultra high density embedded semiconductor die package (2024-11-19),

2. 11676938 - Semiconductor device and method of making wafer level chip scale package (2023-06-13),

3. 11257729 - Semiconductor device and method of forming encapsulated wafer level chip scale package (eWLCSP) (2022-02-22),

4. 11227809 - Semiconductor device and method of forming ultra high density embedded semiconductor die package (2022-01-18),

5. 11127668 - Semiconductor device and method of forming double-sided fan-out wafer level package (2021-09-21),

6. 10998248 - Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die (2021-05-04),

7. 10916482 - Semiconductor device and method of forming reconstituted wafer with larger carrier to achieve more EWLB packages per wafer with encapsulant deposited under temperature and pressure (2021-02-09),

8. RE48408 - Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect (2021-01-25),

9. 10903183 - Semiconductor device and method of using leadframe bodies to form openings through encapsulant for vertical interconnect of semiconductor die (2021-01-26),

10. RE48111 - Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect (2020-07-20),

11. 10665534 - Semiconductor device and method of using partial wafer singulation for improved wafer level embedded system in package (2020-05-26),

12. 10651139 - Semiconductor device and method of forming wafer level ground plane and power ring (2020-05-12),

13. 10643952 - Semiconductor device and method of forming EMI shielding layer with conductive material around semiconductor die (2020-05-05),

14. 10622293 - Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLB-MLP) (2020-04-14),

15. 10607946 - Semiconductor device and method of forming interconnect substrate for FO-WLCSP (2020-03-31),

JCET Semiconductor (Shaoxing) Co., Ltd. is a leading semiconductor packaging and testing company in China. With state-of-the-art facilities and innovative technologies, JCET Semiconductor offers comprehensive solutions for semiconductor manufacturers worldwide. They specialize in advanced packaging, wafer-level packaging, and testing services. Their commitment to quality, reliability, and customer satisfaction has earned them a strong reputation in the industry. For more information, please visit their website.

This text is generated by artificial intelligence and may not be accurate.

Company Badge

USPTO Data Jan 1 1976 - Dec 30 2025

15 Patents

#4 in

#1,708 in

#38,719 in the World

Shaoxing, China

Jcet Semiconductor (Shaoxing) Co., Ltd.

Forward Citations = 5

38 inventors:

Yaojian Lin (4 out of 290 patents)

Reza A Pagaila (4 out of 192 patents)

Yung Kuan Hsiao (3 out of 11 patents)

4. Yoke Hor Phua (3 out of 6 patents)

5. Seung Uk Yoon (3 out of 17 patents)

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