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For the Inventor, By the Inventor

Singapore, Singapore

Jianmin Fang

This inventor holds 59 USPTO granted patents, primarily in Semiconductor Devices (CPC class H01L). Top assignees: Stats Chippac Pte. Ltd., Jcet Semiconductor (Shaoxing) Co., Ltd., Chengdu Kanghong Biotechnologies Co., Ltd.. Active years: 2010-2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jianmin Fang. Retrieved from https://idiyas.com/inventor/jianmin-fang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 59

% Patents Active = 100.0

Average Co-Inventor Count = 4.1

ph-index = 13

Forward Citations = 794(Granted Patents)

Forward Citations (Not Self Cited) = 754(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Singapore, SG (2010 - 2021)
  • Shanghai, CN (2010 - 2021)

Company Filing History:

goldMedal55 out of 1,845 
 
Stats Chippac Pte. Ltd.
 patents
silverMedal2 out of 15 
 
Jcet Semiconductor (Shaoxing) Co., Ltd.
 patents
bronzeMedal1 out of 6 
 
Chengdu Kanghong Biotechnologies Co., Ltd.
 patents
4. 1 out of 2 
 
Shanghai Tongji Hospital
 patents

Years Active: 2010-2021

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Areas of Expertise:
Semiconductor Device
Interconnect Structure
Embedded Wafer Level Package
Integrated Passive Device
Repassivation Layer
Fan-Out Structure
Conductive Channels
Vertical Interconnect
Silicon Vias
Bump Structure
Insulating Layer
Protective Structure
59 patents (USPTO):Explore Patents
1. 11127666 - Semiconductor device and method of forming openings through insulating layer over encapsulant for enhanced adhesion of interconnect structure (2021-09-21),
2. 11066476 - Asymmetric bispecific antibody (2021-07-20),
3. 10622293 - Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLB-MLP) (2020-04-14),
4. 10607946 - Semiconductor device and method of forming interconnect substrate for FO-WLCSP (2020-03-31),
5. 10211183 - Semiconductor device and method of forming shielding layer over integrated passive device using conductive channels (2019-02-19),
6. 10204866 - Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation (2019-02-12),
7. 10192801 - Semiconductor device and method of forming vertical interconnect structure in substrate for IPD and baseband circuit separated by high-resistivity molding compound (2019-01-29),
8. 10163815 - Semiconductor device with dummy metal protective structure around semiconductor die for localized planarization of insulating layer (2018-12-25),
9. 9865482 - Semiconductor device and method of forming a fan-out structure with integrated passive device and discrete component (2018-01-09),
10. 9754867 - Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package (2017-09-05),
11. 9679863 - Semiconductor device and method of forming interconnect substrate for FO-WLCSP (2017-06-13),
12. 9666500 - Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief (2017-05-30),
13. 9601434 - Semiconductor device and method of forming openings through insulating layer over encapsulant for enhanced adhesion of interconnect structure (2017-03-21),
14. 9558958 - Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation (2017-01-31),
15. 9548240 - Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package (2017-01-17),

Title: Jianmin Fang: Leading Innovations in Semiconductor Technology

Introduction

Jianmin Fang, an accomplished inventor based in Singapore, has made significant contributions to the field of semiconductor technology. With a remarkable portfolio of 59 patents, Fang's work embodies innovation and forward-thinking in various applications. His latest patents reflect the advanced methodologies he employs to enhance semiconductor devices and biomedical applications.

Latest Patents

Among Jianmin Fang's notable recent patents is a groundbreaking invention titled "Semiconductor device and method of forming openings through insulating layer over encapsulant for enhanced adhesion of interconnect structure." This patent describes a semiconductor device comprising a semiconductor die mounted on a carrier, with an encapsulant applied over the die and carrier. The process includes forming an insulating layer over the encapsulant within an interconnect site and creating openings to expose the encapsulant, facilitating improved adhesion for interconnect structures.

Another significant patent is related to an "Asymmetric bispecific antibody." This innovative invention addresses the preparation methods and therapeutic applications of this novel antibody, showcasing Fang's expertise in both semiconductor technology and biomedicine.

Career Highlights

Jianmin Fang has had a distinguished career, working with reputable companies such as Stats Chippac Pte. Ltd. and Jcet Semiconductor (Shaoxing) Co., Ltd. His contributions to these organizations highlight his capacity to drive advancements in semiconductors effectively.

Collaborations

Throughout his career, Fang has collaborated with talented individuals, including coworkers Yaojian Lin and Kang Chen. These partnerships have likely fostered an environment of innovation, allowing for the exchange of ideas and expertise that further enhances the development of cutting-edge technologies.

Conclusion

In summary, Jianmin Fang stands out as a leading inventor in semiconductor technology, renowned for his innovative approaches and significant contributions through his numerous patents. As technology continues to evolve, his work will undoubtedly leave a lasting impact on both the semiconductor industry and the fields of biomedical research.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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