The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2017
Filed:
Apr. 27, 2015
Stats Chippac, Ltd., Singapore, SG;
Yaojian Lin, Singapore, SG;
Pandi C. Marimuthu, Singapore, SG;
Kang Chen, Singapore, SG;
Hin Hwa Goh, Singapore, SG;
Yu Gu, Singapore, SG;
Il Kwon Shim, Singapore, SG;
Rui Huang, Singapore, SG;
Seng Guan Chow, Singapore, SG;
Jianmin Fang, Shanghai, CN;
Xia Feng, Shanghai, CN;
STATS ChipPAC Pte. Ltd., Singapore, SG;
Abstract
A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.